scanwave.map.eqn

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

--operation mode is normal

H1_RAMTMP7[6]_lut_out = A1L94 & (H1L79 # H1_RAMTMP7[6] & X1_q_a[3]) # !A1L94 & H1_RAMTMP7[6] & X1_q_a[3];
H1_RAMTMP7[6] = DFFEA(H1_RAMTMP7[6]_lut_out, !CLK, VCC, , H1L92, , );


--N1_ADOUT_A[6] is MAX114:inst11|ADOUT_A[6]
--operation mode is normal

N1_ADOUT_A[6]_lut_out = ADIN[6];
N1_ADOUT_A[6] = DFFEA(N1_ADOUT_A[6]_lut_out, CLK, VCC, , N1L62, , );


--H1_RAMTMP7[2] is BUS_1:inst5|RAMTMP7[2]
--operation mode is normal

H1_RAMTMP7[2]_lut_out = A1L35 & (H1L79 # H1_RAMTMP7[2] & X1_q_a[3]) # !A1L35 & H1_RAMTMP7[2] & X1_q_a[3];
H1_RAMTMP7[2] = DFFEA(H1_RAMTMP7[2]_lut_out, !CLK, VCC, , H1L92, , );


--N1_ADOUT_A[2] is MAX114:inst11|ADOUT_A[2]
--operation mode is normal

N1_ADOUT_A[2]_lut_out = ADIN[2];
N1_ADOUT_A[2] = DFFEA(N1_ADOUT_A[2]_lut_out, CLK, VCC, , N1L62, , );


--S1L14 is CONV_SINGLE:inst22|reduce_nor~42
--operation mode is normal

S1L14 = H1_RAMTMP7[6] & (H1_RAMTMP7[2] $ N1_ADOUT_A[2] # !N1_ADOUT_A[6]) # !H1_RAMTMP7[6] & (N1_ADOUT_A[6] # H1_RAMTMP7[2] $ N1_ADOUT_A[2]);


--S1L24 is CONV_SINGLE:inst22|reduce_nor~43
--operation mode is normal

S1L24 = S1L83 # S1L93 # S1L04 # S1L14;


--L1L82 is VOLTAGE_CONV:inst9|LessThan~7
--operation mode is arithmetic

L1L82 = CARRY(L1L31 & V1_q_b[6] & !L1L62 # !L1L31 & (V1_q_b[6] # !L1L62));


--V2_q_b[7] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
V2_q_b[7]_PORT_A_data_in = R2_data[7];
V2_q_b[7]_PORT_A_data_in_reg = DFFE(V2_q_b[7]_PORT_A_data_in, V2_q_b[7]_clock_0, , , );
V2_q_b[7]_PORT_A_address = BUS(R2_cnt2[0], R2_cnt2[1], R2_cnt2[2], R2_cnt2[3], R2_cnt2[4], R2_cnt2[5], R2_cnt2[6], R2_cnt2[7], R2_cnt2[8], R2_cnt2[9], R2_cnt2[10]);
V2_q_b[7]_PORT_A_address_reg = DFFE(V2_q_b[7]_PORT_A_address, V2_q_b[7]_clock_0, , , );
V2_q_b[7]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V2_q_b[7]_PORT_B_address_reg = DFFE(V2_q_b[7]_PORT_B_address, V2_q_b[7]_clock_1, , , );
V2_q_b[7]_PORT_A_write_enable = VCC;
V2_q_b[7]_PORT_A_write_enable_reg = DFFE(V2_q_b[7]_PORT_A_write_enable, V2_q_b[7]_clock_0, , , );
V2_q_b[7]_PORT_B_read_enable = VCC;
V2_q_b[7]_PORT_B_read_enable_reg = DFFE(V2_q_b[7]_PORT_B_read_enable, V2_q_b[7]_clock_1, , , );
V2_q_b[7]_clock_0 = CLK;
V2_q_b[7]_clock_1 = CLK;
V2_q_b[7]_PORT_B_data_out = MEMORY(V2_q_b[7]_PORT_A_data_in_reg, , V2_q_b[7]_PORT_A_address_reg, V2_q_b[7]_PORT_B_address_reg, V2_q_b[7]_PORT_A_write_enable_reg, V2_q_b[7]_PORT_B_read_enable_reg, , , V2_q_b[7]_clock_0, V2_q_b[7]_clock_1, , , , );
V2_q_b[7] = V2_q_b[7]_PORT_B_data_out[0];


--H1_RAMTMP5[7] is BUS_1:inst5|RAMTMP5[7]
--operation mode is normal

H1_RAMTMP5[7]_lut_out = A1L84 & (H1L69 # H1_RAMTMP5[7] & X1_q_a[5]) # !A1L84 & H1_RAMTMP5[7] & X1_q_a[5];
H1_RAMTMP5[7] = DFFEA(H1_RAMTMP5[7]_lut_out, !CLK, VCC, , H1L92, , );


--L2L82 is VOLTAGE_CONV:inst17|LessThan~7
--operation mode is arithmetic

L2L82 = CARRY(L2L31 & V2_q_b[6] & !L2L62 # !L2L31 & (V2_q_b[6] # !L2L62));


--V1_q_b[6] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_b[6]_PORT_A_data_in = R1_data[6];
V1_q_b[6]_PORT_A_data_in_reg = DFFE(V1_q_b[6]_PORT_A_data_in, V1_q_b[6]_clock_0, , , );
V1_q_b[6]_PORT_A_address = BUS(R1_cnt2[0], R1_cnt2[1], R1_cnt2[2], R1_cnt2[3], R1_cnt2[4], R1_cnt2[5], R1_cnt2[6], R1_cnt2[7], R1_cnt2[8], R1_cnt2[9], R1_cnt2[10]);
V1_q_b[6]_PORT_A_address_reg = DFFE(V1_q_b[6]_PORT_A_address, V1_q_b[6]_clock_0, , , );
V1_q_b[6]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V1_q_b[6]_PORT_B_address_reg = DFFE(V1_q_b[6]_PORT_B_address, V1_q_b[6]_clock_1, , , );
V1_q_b[6]_PORT_A_write_enable = VCC;
V1_q_b[6]_PORT_A_write_enable_reg = DFFE(V1_q_b[6]_PORT_A_write_enable, V1_q_b[6]_clock_0, , , );
V1_q_b[6]_PORT_B_read_enable = VCC;
V1_q_b[6]_PORT_B_read_enable_reg = DFFE(V1_q_b[6]_PORT_B_read_enable, V1_q_b[6]_clock_1, , , );
V1_q_b[6]_clock_0 = CLK;
V1_q_b[6]_clock_1 = CLK;
V1_q_b[6]_PORT_B_data_out = MEMORY(V1_q_b[6]_PORT_A_data_in_reg, , V1_q_b[6]_PORT_A_address_reg, V1_q_b[6]_PORT_B_address_reg, V1_q_b[6]_PORT_A_write_enable_reg, V1_q_b[6]_PORT_B_read_enable_reg, , , V1_q_b[6]_clock_0, V1_q_b[6]_clock_1, , , , );
V1_q_b[6] = V1_q_b[6]_PORT_B_data_out[0];


--H1_RAMTMP2[6] is BUS_1:inst5|RAMTMP2[6]
--operation mode is normal

H1_RAMTMP2[6]_lut_out = A1L94 & (H1L59 # H1_RAMTMP2[6] & X1_q_a[6]) # !A1L94 & H1_RAMTMP2[6] & X1_q_a[6];
H1_RAMTMP2[6] = DFFEA(H1_RAMTMP2[6]_lut_out, !CLK, VCC, , H1L92, , );


--V2_q_b[6] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
V2_q_b[6]_PORT_A_data_in = R2_data[6];
V2_q_b[6]_PORT_A_data_in_reg = DFFE(V2_q_b[6]_PORT_A_data_in, V2_q_b[6]_clock_0, , , );
V2_q_b[6]_PORT_A_address = BUS(R2_cnt2[0], R2_cnt2[1], R2_cnt2[2], R2_cnt2[3], R2_cnt2[4], R2_cnt2[5], R2_cnt2[6], R2_cnt2[7], R2_cnt2[8], R2_cnt2[9], R2_cnt2[10]);
V2_q_b[6]_PORT_A_address_reg = DFFE(V2_q_b[6]_PORT_A_address, V2_q_b[6]_clock_0, , , );
V2_q_b[6]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V2_q_b[6]_PORT_B_address_reg = DFFE(V2_q_b[6]_PORT_B_address, V2_q_b[6]_clock_1, , , );
V2_q_b[6]_PORT_A_write_enable = VCC;
V2_q_b[6]_PORT_A_write_enable_reg = DFFE(V2_q_b[6]_PORT_A_write_enable, V2_q_b[6]_clock_0, , , );
V2_q_b[6]_PORT_B_read_enable = VCC;
V2_q_b[6]_PORT_B_read_enable_reg = DFFE(V2_q_b[6]_PORT_B_read_enable, V2_q_b[6]_clock_1, , , );
V2_q_b[6]_clock_0 = CLK;
V2_q_b[6]_clock_1 = CLK;
V2_q_b[6]_PORT_B_data_out = MEMORY(V2_q_b[6]_PORT_A_data_in_reg, , V2_q_b[6]_PORT_A_address_reg, V2_q_b[6]_PORT_B_address_reg, V2_q_b[6]_PORT_A_write_enable_reg, V2_q_b[6]_PORT_B_read_enable_reg, , , V2_q_b[6]_clock_0, V2_q_b[6]_clock_1, , , , );
V2_q_b[6] = V2_q_b[6]_PORT_B_data_out[0];


--H1_RAMTMP5[6] is BUS_1:inst5|RAMTMP5[6]
--operation mode is normal

H1_RAMTMP5[6]_lut_out = A1L94 & (H1L69 # H1_RAMTMP5[6] & X1_q_a[5]) # !A1L94 & H1_RAMTMP5[6] & X1_q_a[5];
H1_RAMTMP5[6] = DFFEA(H1_RAMTMP5[6]_lut_out, !CLK, VCC, , H1L92, , );


--V1_q_b[5] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_b[5]_PORT_A_data_in = R1_data[5];
V1_q_b[5]_PORT_A_data_in_reg = DFFE(V1_q_b[5]_PORT_A_data_in, V1_q_b[5]_clock_0, , , );
V1_q_b[5]_PORT_A_address = BUS(R1_cnt2[0], R1_cnt2[1], R1_cnt2[2], R1_cnt2[3], R1_cnt2[4], R1_cnt2[5], R1_cnt2[6], R1_cnt2[7], R1_cnt2[8], R1_cnt2[9], R1_cnt2[10]);
V1_q_b[5]_PORT_A_address_reg = DFFE(V1_q_b[5]_PORT_A_address, V1_q_b[5]_clock_0, , , );
V1_q_b[5]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V1_q_b[5]_PORT_B_address_reg = DFFE(V1_q_b[5]_PORT_B_address, V1_q_b[5]_clock_1, , , );
V1_q_b[5]_PORT_A_write_enable = VCC;
V1_q_b[5]_PORT_A_write_enable_reg = DFFE(V1_q_b[5]_PORT_A_write_enable, V1_q_b[5]_clock_0, , , );
V1_q_b[5]_PORT_B_read_enable = VCC;
V1_q_b[5]_PORT_B_read_enable_reg = DFFE(V1_q_b[5]_PORT_B_read_enable, V1_q_b[5]_clock_1, , , );
V1_q_b[5]_clock_0 = CLK;
V1_q_b[5]_clock_1 = CLK;
V1_q_b[5]_PORT_B_data_out = MEMORY(V1_q_b[5]_PORT_A_data_in_reg, , V1_q_b[5]_PORT_A_address_reg, V1_q_b[5]_PORT_B_address_reg, V1_q_b[5]_PORT_A_write_enable_reg, V1_q_b[5]_PORT_B_read_enable_reg, , , V1_q_b[5]_clock_0, V1_q_b[5]_clock_1, , , , );
V1_q_b[5] = V1_q_b[5]_PORT_B_data_out[0];


--H1_RAMTMP2[5] is BUS_1:inst5|RAMTMP2[5]
--operation mode is normal

H1_RAMTMP2[5]_lut_out = A1L05 & (H1L59 # H1_RAMTMP2[5] & X1_q_a[6]) # !A1L05 & H1_RAMTMP2[5] & X1_q_a[6];
H1_RAMTMP2[5] = DFFEA(H1_RAMTMP2[5]_lut_out, !CLK, VCC, , H1L92, , );


--V2_q_b[5] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
V2_q_b[5]_PORT_A_data_in = R2_data[5];
V2_q_b[5]_PORT_A_data_in_reg = DFFE(V2_q_b[5]_PORT_A_data_in, V2_q_b[5]_clock_0, , , );
V2_q_b[5]_PORT_A_address = BUS(R2_cnt2[0], R2_cnt2[1], R2_cnt2[2], R2_cnt2[3], R2_cnt2[4], R2_cnt2[5], R2_cnt2[6], R2_cnt2[7], R2_cnt2[8], R2_cnt2[9], R2_cnt2[10]);
V2_q_b[5]_PORT_A_address_reg = DFFE(V2_q_b[5]_PORT_A_address, V2_q_b[5]_clock_0, , , );
V2_q_b[5]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V2_q_b[5]_PORT_B_address_reg = DFFE(V2_q_b[5]_PORT_B_address, V2_q_b[5]_clock_1, , , );
V2_q_b[5]_PORT_A_write_enable = VCC;
V2_q_b[5]_PORT_A_write_enable_reg = DFFE(V2_q_b[5]_PORT_A_write_enable, V2_q_b[5]_clock_0, , , );
V2_q_b[5]_PORT_B_read_enable = VCC;
V2_q_b[5]_PORT_B_read_enable_reg = DFFE(V2_q_b[5]_PORT_B_read_enable, V2_q_b[5]_clock_1, , , );
V2_q_b[5]_clock_0 = CLK;
V2_q_b[5]_clock_1 = CLK;
V2_q_b[5]_PORT_B_data_out = MEMORY(V2_q_b[5]_PORT_A_data_in_reg, , V2_q_b[5]_PORT_A_address_reg, V2_q_b[5]_PORT_B_address_reg, V2_q_b[5]_PORT_A_write_enable_reg, V2_q_b[5]_PORT_B_read_enable_reg, , , V2_q_b[5]_clock_0, V2_q_b[5]_clock_1, , , , );
V2_q_b[5] = V2_q_b[5]_PORT_B_data_out[0];


--H1_RAMTMP5[5] is BUS_1:inst5|RAMTMP5[5]
--operation mode is normal

H1_RAMTMP5[5]_lut_out = A1L05 & (H1L69 # H1_RAMTMP5[5] & X1_q_a[5]) # !A1L05 & H1_RAMTMP5[5] & X1_q_a[5];
H1_RAMTMP5[5] = DFFEA(H1_RAMTMP5[5]_lut_out, !CLK, VCC, , H1L92, , );


--V1_q_b[4] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_b[4]_PORT_A_data_in = R1_data[4];
V1_q_b[4]_PORT_A_data_in_reg = DFFE(V1_q_b[4]_PORT_A_data_in, V1_q_b[4]_clock_0, , , );
V1_q_b[4]_PORT_A_address = BUS(R1_cnt2[0], R1_cnt2[1], R1_cnt2[2], R1_cnt2[3], R1_cnt2[4], R1_cnt2[5], R1_cnt2[6], R1_cnt2[7], R1_cnt2[8], R1_cnt2[9], R1_cnt2[10]);
V1_q_b[4]_PORT_A_address_reg = DFFE(V1_q_b[4]_PORT_A_address, V1_q_b[4]_clock_0, , , );
V1_q_b[4]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V1_q_b[4]_PORT_B_address_reg = DFFE(V1_q_b[4]_PORT_B_address, V1_q_b[4]_clock_1, , , );
V1_q_b[4]_PORT_A_write_enable = VCC;
V1_q_b[4]_PORT_A_write_enable_reg = DFFE(V1_q_b[4]_PORT_A_write_enable, V1_q_b[4]_clock_0, , , );
V1_q_b[4]_PORT_B_read_enable = VCC;
V1_q_b[4]_PORT_B_read_enable_reg = DFFE(V1_q_b[4]_PORT_B_read_enable, V1_q_b[4]_clock_1, , , );
V1_q_b[4]_clock_0 = CLK;
V1_q_b[4]_clock_1 = CLK;
V1_q_b[4]_PORT_B_data_out = MEMORY(V1_q_b[4]_PORT_A_data_in_reg, , V1_q_b[4]_PORT_A_address_reg, V1_q_b[4]_PORT_B_address_reg, V1_q_b[4]_PORT_A_write_enable_reg, V1_q_b[4]_PORT_B_read_enable_reg, , , V1_q_b[4]_clock_0, V1_q_b[4]_clock_1, , , , );
V1_q_b[4] = V1_q_b[4]_PORT_B_data_out[0];


--H1_RAMTMP2[4] is BUS_1:inst5|RAMTMP2[4]
--operation mode is normal

H1_RAMTMP2[4]_lut_out = A1L15 & (H1L59 # H1_RAMTMP2[4] & X1_q_a[6]) # !A1L15 & H1_RAMTMP2[4] & X1_q_a[6];
H1_RAMTMP2[4] = DFFEA(H1_RAMTMP2[4]_lut_out, !CLK, VCC, , H1L92, , );


--V2_q_b[4] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
V2_q_b[4]_PORT_A_data_in = R2_data[4];
V2_q_b[4]_PORT_A_data_in_reg = DFFE(V2_q_b[4]_PORT_A_data_in, V2_q_b[4]_clock_0, , , );
V2_q_b[4]_PORT_A_address = BUS(R2_cnt2[0], R2_cnt2[1], R2_cnt2[2], R2_cnt2[3], R2_cnt2[4], R2_cnt2[5], R2_cnt2[6], R2_cnt2[7], R2_cnt2[8], R2_cnt2[9], R2_cnt2[10]);
V2_q_b[4]_PORT_A_address_reg = DFFE(V2_q_b[4]_PORT_A_address, V2_q_b[4]_clock_0, , , );
V2_q_b[4]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V2_q_b[4]_PORT_B_address_reg = DFFE(V2_q_b[4]_PORT_B_address, V2_q_b[4]_clock_1, , , );
V2_q_b[4]_PORT_A_write_enable = VCC;
V2_q_b[4]_PORT_A_write_enable_reg = DFFE(V2_q_b[4]_PORT_A_write_enable, V2_q_b[4]_clock_0, , , );
V2_q_b[4]_PORT_B_read_enable = VCC;
V2_q_b[4]_PORT_B_read_enable_reg = DFFE(V2_q_b[4]_PORT_B_read_enable, V2_q_b[4]_clock_1, , , );
V2_q_b[4]_clock_0 = CLK;
V2_q_b[4]_clock_1 = CLK;
V2_q_b[4]_PORT_B_data_out = MEMORY(V2_q_b[4]_PORT_A_data_in_reg, , V2_q_b[4]_PORT_A_address_reg, V2_q_b[4]_PORT_B_address_reg, V2_q_b[4]_PORT_A_write_enable_reg, V2_q_b[4]_PORT_B_read_enable_reg, , , V2_q_b[4]_clock_0, V2_q_b[4]_clock_1, , , , );
V2_q_b[4] = V2_q_b[4]_PORT_B_data_out[0];


--H1_RAMTMP5[4] is BUS_1:inst5|RAMTMP5[4]
--operation mode is normal

H1_RAMTMP5[4]_lut_out = A1L15 & (H1L69 # H1_RAMTMP5[4] & X1_q_a[5]) # !A1L15 & H1_RAMTMP5[4] & X1_q_a[5];
H1_RAMTMP5[4] = DFFEA(H1_RAMTMP5[4]_lut_out, !CLK, VCC, , H1L92, , );


--V1_q_b[3] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_b[3]_PORT_A_data_in = R1_data[3];
V1_q_b[3]_PORT_A_data_in_reg = DFFE(V1_q_b[3]_PORT_A_data_in, V1_q_b[3]_clock_0, , , );
V1_q_b[3]_PORT_A_address = BUS(R1_cnt2[0], R1_cnt2[1], R1_cnt2[2], R1_cnt2[3], R1_cnt2[4], R1_cnt2[5], R1_cnt2[6], R1_cnt2[7], R1_cnt2[8], R1_cnt2[9], R1_cnt2[10]);
V1_q_b[3]_PORT_A_address_reg = DFFE(V1_q_b[3]_PORT_A_address, V1_q_b[3]_clock_0, , , );
V1_q_b[3]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V1_q_b[3]_PORT_B_address_reg = DFFE(V1_q_b[3]_PORT_B_address, V1_q_b[3]_clock_1, , , );
V1_q_b[3]_PORT_A_write_enable = VCC;
V1_q_b[3]_PORT_A_write_enable_reg = DFFE(V1_q_b[3]_PORT_A_write_enable, V1_q_b[3]_clock_0, , , );
V1_q_b[3]_PORT_B_read_enable = VCC;
V1_q_b[3]_PORT_B_read_enable_reg = DFFE(V1_q_b[3]_PORT_B_read_enable, V1_q_b[3]_clock_1, , , );
V1_q_b[3]_clock_0 = CLK;
V1_q_b[3]_clock_1 = CLK;
V1_q_b[3]_PORT_B_data_out = MEMORY(V1_q_b[3]_PORT_A_data_in_reg, , V1_q_b[3]_PORT_A_address_reg, V1_q_b[3]_PORT_B_address_reg, V1_q_b[3]_PORT_A_write_enable_reg, V1_q_b[3]_PORT_B_read_enable_reg, , , V1_q_b[3]_clock_0, V1_q_b[3]_clock_1, , , , );
V1_q_b[3] = V1_q_b[3]_PORT_B_data_out[0];


--H1_RAMTMP2[3] is BUS_1:inst5|RAMTMP2[3]
--operation mode is normal

H1_RAMTMP2[3]_lut_out = A1L25 & (H1L59 # H1_RAMTMP2[3] & X1_q_a[6]) # !A1L25 & H1_RAMTMP2[3] & X1_q_a[6];
H1_RAMTMP2[3] = DFFEA(H1_RAMTMP2[3]_lut_out, !CLK, VCC, , H1L92, , );


--V2_q_b[3] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
V2_q_b[3]_PORT_A_data_in = R2_data[3];
V2_q_b[3]_PORT_A_data_in_reg = DFFE(V2_q_b[3]_PORT_A_data_in, V2_q_b[3]_clock_0, , , );
V2_q_b[3]_PORT_A_address = BUS(R2_cnt2[0], R2_cnt2[1], R2_cnt2[2], R2_cnt2[3], R2_cnt2[4], R2_cnt2[5], R2_cnt2[6], R2_cnt2[7], R2_cnt2[8], R2_cnt2[9], R2_cnt2[10]);
V2_q_b[3]_PORT_A_address_reg = DFFE(V2_q_b[3]_PORT_A_address, V2_q_b[3]_clock_0, , , );
V2_q_b[3]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V2_q_b[3]_PORT_B_address_reg = DFFE(V2_q_b[3]_PORT_B_address, V2_q_b[3]_clock_1, , , );
V2_q_b[3]_PORT_A_write_enable = VCC;
V2_q_b[3]_PORT_A_write_enable_reg = DFFE(V2_q_b[3]_PORT_A_write_enable, V2_q_b[3]_clock_0, , , );
V2_q_b[3]_PORT_B_read_enable = VCC;
V2_q_b[3]_PORT_B_read_enable_reg = DFFE(V2_q_b[3]_PORT_B_read_enable, V2_q_b[3]_clock_1, , , );
V2_q_b[3]_clock_0 = CLK;
V2_q_b[3]_clock_1 = CLK;
V2_q_b[3]_PORT_B_data_out = MEMORY(V2_q_b[3]_PORT_A_data_in_reg, , V2_q_b[3]_PORT_A_address_reg, V2_q_b[3]_PORT_B_address_reg, V2_q_b[3]_PORT_A_write_enable_reg, V2_q_b[3]_PORT_B_read_enable_reg, , , V2_q_b[3]_clock_0, V2_q_b[3]_clock_1, , , , );
V2_q_b[3] = V2_q_b[3]_PORT_B_data_out[0];


--H1_RAMTMP5[3] is BUS_1:inst5|RAMTMP5[3]
--operation mode is normal

H1_RAMTMP5[3]_lut_out = A1L25 & (H1L69 # H1_RAMTMP5[3] & X1_q_a[5]) # !A1L25 & H1_RAMTMP5[3] & X1_q_a[5];
H1_RAMTMP5[3] = DFFEA(H1_RAMTMP5[3]_lut_out, !CLK, VCC, , H1L92, , );


--V1_q_b[2] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_b[2]_PORT_A_data_in = R1_data[2];
V1_q_b[2]_PORT_A_data_in_reg = DFFE(V1_q_b[2]_PORT_A_data_in, V1_q_b[2]_clock_0, , , );
V1_q_b[2]_PORT_A_address = BUS(R1_cnt2[0], R1_cnt2[1], R1_cnt2[2], R1_cnt2[3], R1_cnt2[4], R1_cnt2[5], R1_cnt2[6], R1_cnt2[7], R1_cnt2[8], R1_cnt2[9], R1_cnt2[10]);
V1_q_b[2]_PORT_A_address_reg = DFFE(V1_q_b[2]_PORT_A_address, V1_q_b[2]_clock_0, , , );
V1_q_b[2]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V1_q_b[2]_PORT_B_address_reg = DFFE(V1_q_b[2]_PORT_B_address, V1_q_b[2]_clock_1, , , );
V1_q_b[2]_PORT_A_write_enable = VCC;
V1_q_b[2]_PORT_A_write_enable_reg = DFFE(V1_q_b[2]_PORT_A_write_enable, V1_q_b[2]_clock_0, , , );
V1_q_b[2]_PORT_B_read_enable = VCC;
V1_q_b[2]_PORT_B_read_enable_reg = DFFE(V1_q_b[2]_PORT_B_read_enable, V1_q_b[2]_clock_1, , , );
V1_q_b[2]_clock_0 = CLK;
V1_q_b[2]_clock_1 = CLK;
V1_q_b[2]_PORT_B_data_out = MEMORY(V1_q_b[2]_PORT_A_data_in_reg, , V1_q_b[2]_PORT_A_address_reg, V1_q_b[2]_PORT_B_address_reg, V1_q_b[2]_PORT_A_write_enable_reg, V1_q_b[2]_PORT_B_read_enable_reg, , , V1_q_b[2]_clock_0, V1_q_b[2]_clock_1, , , , );
V1_q_b[2] = V1_q_b[2]_PORT_B_data_out[0];


--H1_RAMTMP2[2] is BUS_1:inst5|RAMTMP2[2]
--operation mode is normal

H1_RAMTMP2[2]_lut_out = A1L35 & (H1L59 # H1_RAMTMP2[2] & X1_q_a[6]) # !A1L35 & H1_RAMTMP2[2] & X1_q_a[6];
H1_RAMTMP2[2] = DFFEA(H1_RAMTMP2[2]_lut_out, !CLK, VCC, , H1L92, , );


--V2_q_b[2] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8