scanwave.map.eqn

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

--L2L8 is VOLTAGE_CONV:inst17|add~4COUT
--operation mode is arithmetic

L2L8 = CARRY(V2_q_b[3] & !H1_RAMTMP5[3] & !L2L6 # !V2_q_b[3] & (!L2L6 # !H1_RAMTMP5[3]));


--L1L5 is VOLTAGE_CONV:inst9|add~3
--operation mode is arithmetic

L1L5_carry_eqn = L1L4;
L1L5 = V1_q_b[2] $ H1_RAMTMP2[2] $ !L1L5_carry_eqn;

--L1L6 is VOLTAGE_CONV:inst9|add~3COUT
--operation mode is arithmetic

L1L6 = CARRY(V1_q_b[2] & (H1_RAMTMP2[2] # !L1L4) # !V1_q_b[2] & H1_RAMTMP2[2] & !L1L4);


--L2L5 is VOLTAGE_CONV:inst17|add~3
--operation mode is arithmetic

L2L5_carry_eqn = L2L4;
L2L5 = V2_q_b[2] $ H1_RAMTMP5[2] $ !L2L5_carry_eqn;

--L2L6 is VOLTAGE_CONV:inst17|add~3COUT
--operation mode is arithmetic

L2L6 = CARRY(V2_q_b[2] & (H1_RAMTMP5[2] # !L2L4) # !V2_q_b[2] & H1_RAMTMP5[2] & !L2L4);


--L1L3 is VOLTAGE_CONV:inst9|add~2
--operation mode is arithmetic

L1L3_carry_eqn = L1L2;
L1L3 = V1_q_b[1] $ H1_RAMTMP2[1] $ L1L3_carry_eqn;

--L1L4 is VOLTAGE_CONV:inst9|add~2COUT
--operation mode is arithmetic

L1L4 = CARRY(V1_q_b[1] & !H1_RAMTMP2[1] & !L1L2 # !V1_q_b[1] & (!L1L2 # !H1_RAMTMP2[1]));


--L2L3 is VOLTAGE_CONV:inst17|add~2
--operation mode is arithmetic

L2L3_carry_eqn = L2L2;
L2L3 = V2_q_b[1] $ H1_RAMTMP5[1] $ L2L3_carry_eqn;

--L2L4 is VOLTAGE_CONV:inst17|add~2COUT
--operation mode is arithmetic

L2L4 = CARRY(V2_q_b[1] & !H1_RAMTMP5[1] & !L2L2 # !V2_q_b[1] & (!L2L2 # !H1_RAMTMP5[1]));


--L1L1 is VOLTAGE_CONV:inst9|add~1
--operation mode is arithmetic

L1L1 = V1_q_b[0] $ H1_RAMTMP2[0];

--L1L2 is VOLTAGE_CONV:inst9|add~1COUT
--operation mode is arithmetic

L1L2 = CARRY(V1_q_b[0] & H1_RAMTMP2[0]);


--L2L1 is VOLTAGE_CONV:inst17|add~1
--operation mode is arithmetic

L2L1 = V2_q_b[0] $ H1_RAMTMP5[0];

--L2L2 is VOLTAGE_CONV:inst17|add~1COUT
--operation mode is arithmetic

L2L2 = CARRY(V2_q_b[0] & H1_RAMTMP5[0]);


--N1L1 is MAX114:inst11|add~56
--operation mode is normal

N1L1 = N1_cnt[1] & N1_cnt[0];


--N1L03 is MAX114:inst11|Mux~321
--operation mode is normal

N1L03 = N1_cnt[1] & N1_cnt[2] & N1_cnt[0];


--K1_COUNTER[1] is FREDEVIDER8:inst8|COUNTER[1]
--operation mode is normal

K1_COUNTER[1]_lut_out = K1_COUNTER[1] & !K1_COUNTER[0] # !K1_COUNTER[1] & !K1_COUNTER[2] & K1_COUNTER[0];
K1_COUNTER[1] = DFFEA(K1_COUNTER[1]_lut_out, CLK, VCC, , , , );


--K1_COUNTER[0] is FREDEVIDER8:inst8|COUNTER[0]
--operation mode is normal

K1_COUNTER[0]_lut_out = !K1_COUNTER[0];
K1_COUNTER[0] = DFFEA(K1_COUNTER[0]_lut_out, CLK, VCC, , , , );


--K1_COUNTER[2] is FREDEVIDER8:inst8|COUNTER[2]
--operation mode is normal

K1_COUNTER[2]_lut_out = K1_COUNTER[1] & (K1_COUNTER[2] $ K1_COUNTER[0]) # !K1_COUNTER[1] & K1_COUNTER[2] & !K1_COUNTER[0];
K1_COUNTER[2] = DFFEA(K1_COUNTER[2]_lut_out, CLK, VCC, , , , );


--K1L6 is FREDEVIDER8:inst8|reduce_nor~14
--operation mode is normal

K1L6 = !K1_COUNTER[1] & K1_COUNTER[0] & K1_COUNTER[2];


--H1L101 is BUS_1:inst5|reduce_nor~160
--operation mode is normal

H1L101 = H1L99 & H1_LATCH_ADDRES[2] & H1_LATCH_ADDRES[3] & H1_LATCH_ADDRES[0];


--X1_q_a[0] is BUS_1:inst5|altsyncram:reduce_or_rtl_1|altsyncram_ccj:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
X1_q_a[0]_PORT_A_address = BUS(A1L94, A1L05, A1L15, A1L25, A1L35, A1L45, A1L55, A1L84);
X1_q_a[0]_PORT_A_address_reg = DFFE(X1_q_a[0]_PORT_A_address, X1_q_a[0]_clock_0, , , );
X1_q_a[0]_clock_0 = !ALE;
X1_q_a[0]_PORT_A_data_out = MEMORY(, , X1_q_a[0]_PORT_A_address_reg, , , , , , X1_q_a[0]_clock_0, , , , , );
X1_q_a[0] = X1_q_a[0]_PORT_A_data_out[0];


--G1L33 is generator_accB:inst4|add~17
--operation mode is arithmetic

G1L33_carry_eqn = G1L23;
G1L33 = G1_REG_Q[16] $ !G1L33_carry_eqn;

--G1L43 is generator_accB:inst4|add~17COUT
--operation mode is arithmetic

G1L43 = CARRY(G1_REG_Q[16] & !G1L23);


--G1L13 is generator_accB:inst4|add~16
--operation mode is arithmetic

G1L13_carry_eqn = G1L03;
G1L13 = G1_REG_Q[15] $ H1_RAMTMP9[7] $ G1L13_carry_eqn;

--G1L23 is generator_accB:inst4|add~16COUT
--operation mode is arithmetic

G1L23 = CARRY(G1_REG_Q[15] & !H1_RAMTMP9[7] & !G1L03 # !G1_REG_Q[15] & (!G1L03 # !H1_RAMTMP9[7]));


--G1L92 is generator_accB:inst4|add~15
--operation mode is arithmetic

G1L92_carry_eqn = G1L82;
G1L92 = G1_REG_Q[14] $ H1_RAMTMP9[6] $ !G1L92_carry_eqn;

--G1L03 is generator_accB:inst4|add~15COUT
--operation mode is arithmetic

G1L03 = CARRY(G1_REG_Q[14] & (H1_RAMTMP9[6] # !G1L82) # !G1_REG_Q[14] & H1_RAMTMP9[6] & !G1L82);


--V1_q_b[7] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_b[7]_PORT_A_data_in = R1_data[7];
V1_q_b[7]_PORT_A_data_in_reg = DFFE(V1_q_b[7]_PORT_A_data_in, V1_q_b[7]_clock_0, , , );
V1_q_b[7]_PORT_A_address = BUS(R1_cnt2[0], R1_cnt2[1], R1_cnt2[2], R1_cnt2[3], R1_cnt2[4], R1_cnt2[5], R1_cnt2[6], R1_cnt2[7], R1_cnt2[8], R1_cnt2[9], R1_cnt2[10]);
V1_q_b[7]_PORT_A_address_reg = DFFE(V1_q_b[7]_PORT_A_address, V1_q_b[7]_clock_0, , , );
V1_q_b[7]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V1_q_b[7]_PORT_B_address_reg = DFFE(V1_q_b[7]_PORT_B_address, V1_q_b[7]_clock_1, , , );
V1_q_b[7]_PORT_A_write_enable = VCC;
V1_q_b[7]_PORT_A_write_enable_reg = DFFE(V1_q_b[7]_PORT_A_write_enable, V1_q_b[7]_clock_0, , , );
V1_q_b[7]_PORT_B_read_enable = VCC;
V1_q_b[7]_PORT_B_read_enable_reg = DFFE(V1_q_b[7]_PORT_B_read_enable, V1_q_b[7]_clock_1, , , );
V1_q_b[7]_clock_0 = CLK;
V1_q_b[7]_clock_1 = CLK;
V1_q_b[7]_PORT_B_data_out = MEMORY(V1_q_b[7]_PORT_A_data_in_reg, , V1_q_b[7]_PORT_A_address_reg, V1_q_b[7]_PORT_B_address_reg, V1_q_b[7]_PORT_A_write_enable_reg, V1_q_b[7]_PORT_B_read_enable_reg, , , V1_q_b[7]_clock_0, V1_q_b[7]_clock_1, , , , );
V1_q_b[7] = V1_q_b[7]_PORT_B_data_out[0];


--H1_RAMTMP2[7] is BUS_1:inst5|RAMTMP2[7]
--operation mode is normal

H1_RAMTMP2[7]_lut_out = A1L84 & (H1L59 # H1_RAMTMP2[7] & X1_q_a[6]) # !A1L84 & H1_RAMTMP2[7] & X1_q_a[6];
H1_RAMTMP2[7] = DFFEA(H1_RAMTMP2[7]_lut_out, !CLK, VCC, , H1L92, , );


--H1_RAMTMP6[0] is BUS_1:inst5|RAMTMP6[0]
--operation mode is normal

H1_RAMTMP6[0]_lut_out = H1_RAMTMP6[0] & (X1_q_a[2] # H1L301 & H1L601) # !H1_RAMTMP6[0] & H1L301 & H1L601;
H1_RAMTMP6[0] = DFFEA(H1_RAMTMP6[0]_lut_out, !CLK, VCC, , H1L92, , );


--S1L4Q is CONV_SINGLE:inst22|CURRENT_STATE~13
--operation mode is normal

S1L4Q_lut_out = S1L63 & (S1L4Q # S1L12 & S1L3Q) # !S1L63 & S1L12 & S1L3Q;
S1L4Q = DFFEA(S1L4Q_lut_out, CLK, VCC, , , , );


--S1L63 is CONV_SINGLE:inst22|LessThan~17
--operation mode is normal

S1L63_carry_eqn = S1L43;
S1L63 = N1_ADOUT_A[7] & S1L75 & S1L63_carry_eqn # !N1_ADOUT_A[7] & (S1L75 # S1L63_carry_eqn);


--S1L73 is CONV_SINGLE:inst22|NEXT_STATE.st0~106
--operation mode is normal

S1L73 = !H1_RAMTMP6[0] & (S1L5Q # !S1L1Q);


--S1L2Q is CONV_SINGLE:inst22|CURRENT_STATE~11
--operation mode is normal

S1L2Q_lut_out = H1_RAMTMP6[0] & (S1L2Q & S1L24 # !S1L1Q);
S1L2Q = DFFEA(S1L2Q_lut_out, CLK, VCC, , , , );


--H1_RAMTMP7[1] is BUS_1:inst5|RAMTMP7[1]
--operation mode is normal

H1_RAMTMP7[1]_lut_out = A1L45 & (H1L79 # H1_RAMTMP7[1] & X1_q_a[3]) # !A1L45 & H1_RAMTMP7[1] & X1_q_a[3];
H1_RAMTMP7[1] = DFFEA(H1_RAMTMP7[1]_lut_out, !CLK, VCC, , H1L92, , );


--N1_ADOUT_A[1] is MAX114:inst11|ADOUT_A[1]
--operation mode is normal

N1_ADOUT_A[1]_lut_out = ADIN[1];
N1_ADOUT_A[1] = DFFEA(N1_ADOUT_A[1]_lut_out, CLK, VCC, , N1L62, , );


--H1_RAMTMP7[7] is BUS_1:inst5|RAMTMP7[7]
--operation mode is normal

H1_RAMTMP7[7]_lut_out = A1L84 & (H1L79 # H1_RAMTMP7[7] & X1_q_a[3]) # !A1L84 & H1_RAMTMP7[7] & X1_q_a[3];
H1_RAMTMP7[7] = DFFEA(H1_RAMTMP7[7]_lut_out, !CLK, VCC, , H1L92, , );


--N1_ADOUT_A[7] is MAX114:inst11|ADOUT_A[7]
--operation mode is normal

N1_ADOUT_A[7]_lut_out = ADIN[7];
N1_ADOUT_A[7] = DFFEA(N1_ADOUT_A[7]_lut_out, CLK, VCC, , N1L62, , );


--S1L83 is CONV_SINGLE:inst22|reduce_nor~39
--operation mode is normal

S1L83 = H1_RAMTMP7[1] & (H1_RAMTMP7[7] $ N1_ADOUT_A[7] # !N1_ADOUT_A[1]) # !H1_RAMTMP7[1] & (N1_ADOUT_A[1] # H1_RAMTMP7[7] $ N1_ADOUT_A[7]);


--H1_RAMTMP7[0] is BUS_1:inst5|RAMTMP7[0]
--operation mode is normal

H1_RAMTMP7[0]_lut_out = A1L55 & (H1L79 # H1_RAMTMP7[0] & X1_q_a[3]) # !A1L55 & H1_RAMTMP7[0] & X1_q_a[3];
H1_RAMTMP7[0] = DFFEA(H1_RAMTMP7[0]_lut_out, !CLK, VCC, , H1L92, , );


--N1_ADOUT_A[0] is MAX114:inst11|ADOUT_A[0]
--operation mode is normal

N1_ADOUT_A[0]_lut_out = ADIN[0];
N1_ADOUT_A[0] = DFFEA(N1_ADOUT_A[0]_lut_out, CLK, VCC, , N1L62, , );


--H1_RAMTMP7[5] is BUS_1:inst5|RAMTMP7[5]
--operation mode is normal

H1_RAMTMP7[5]_lut_out = A1L05 & (H1L79 # H1_RAMTMP7[5] & X1_q_a[3]) # !A1L05 & H1_RAMTMP7[5] & X1_q_a[3];
H1_RAMTMP7[5] = DFFEA(H1_RAMTMP7[5]_lut_out, !CLK, VCC, , H1L92, , );


--N1_ADOUT_A[5] is MAX114:inst11|ADOUT_A[5]
--operation mode is normal

N1_ADOUT_A[5]_lut_out = ADIN[5];
N1_ADOUT_A[5] = DFFEA(N1_ADOUT_A[5]_lut_out, CLK, VCC, , N1L62, , );


--S1L93 is CONV_SINGLE:inst22|reduce_nor~40
--operation mode is normal

S1L93 = H1_RAMTMP7[0] & (H1_RAMTMP7[5] $ N1_ADOUT_A[5] # !N1_ADOUT_A[0]) # !H1_RAMTMP7[0] & (N1_ADOUT_A[0] # H1_RAMTMP7[5] $ N1_ADOUT_A[5]);


--H1_RAMTMP7[3] is BUS_1:inst5|RAMTMP7[3]
--operation mode is normal

H1_RAMTMP7[3]_lut_out = A1L25 & (H1L79 # H1_RAMTMP7[3] & X1_q_a[3]) # !A1L25 & H1_RAMTMP7[3] & X1_q_a[3];
H1_RAMTMP7[3] = DFFEA(H1_RAMTMP7[3]_lut_out, !CLK, VCC, , H1L92, , );


--N1_ADOUT_A[3] is MAX114:inst11|ADOUT_A[3]
--operation mode is normal

N1_ADOUT_A[3]_lut_out = ADIN[3];
N1_ADOUT_A[3] = DFFEA(N1_ADOUT_A[3]_lut_out, CLK, VCC, , N1L62, , );


--H1_RAMTMP7[4] is BUS_1:inst5|RAMTMP7[4]
--operation mode is normal

H1_RAMTMP7[4]_lut_out = A1L15 & (H1L79 # H1_RAMTMP7[4] & X1_q_a[3]) # !A1L15 & H1_RAMTMP7[4] & X1_q_a[3];
H1_RAMTMP7[4] = DFFEA(H1_RAMTMP7[4]_lut_out, !CLK, VCC, , H1L92, , );


--N1_ADOUT_A[4] is MAX114:inst11|ADOUT_A[4]
--operation mode is normal

N1_ADOUT_A[4]_lut_out = ADIN[4];
N1_ADOUT_A[4] = DFFEA(N1_ADOUT_A[4]_lut_out, CLK, VCC, , N1L62, , );


--S1L04 is CONV_SINGLE:inst22|reduce_nor~41
--operation mode is normal

S1L04 = H1_RAMTMP7[3] & (H1_RAMTMP7[4] $ N1_ADOUT_A[4] # !N1_ADOUT_A[3]) # !H1_RAMTMP7[3] & (N1_ADOUT_A[3] # H1_RAMTMP7[4] $ N1_ADOUT_A[4]);


--H1_RAMTMP7[6] is BUS_1:inst5|RAMTMP7[6]