scanwave.map.eqn

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

G1_REG_Q[18]_lut_out = G1L73 & (G1L76 # !G1L34 # !G1L14);
G1_REG_Q[18] = DFFEA(G1_REG_Q[18]_lut_out, K1_CLK, !H1_TMP, , , , );


--G1_REG_Q[17] is generator_accB:inst4|REG_Q[17]
--operation mode is normal

G1_REG_Q[17]_lut_out = G1L53 & (G1L76 # !G1L34 # !G1L14);
G1_REG_Q[17] = DFFEA(G1_REG_Q[17]_lut_out, K1_CLK, !H1_TMP, , , , );


--G1_REG_Q[16] is generator_accB:inst4|REG_Q[16]
--operation mode is normal

G1_REG_Q[16]_lut_out = G1L33 & (G1L76 # !G1L34 # !G1L14);
G1_REG_Q[16] = DFFEA(G1_REG_Q[16]_lut_out, K1_CLK, !H1_TMP, , , , );


--G1_REG_Q[15] is generator_accB:inst4|REG_Q[15]
--operation mode is normal

G1_REG_Q[15]_lut_out = G1L13 & (G1L76 # !G1L34 # !G1L14);
G1_REG_Q[15] = DFFEA(G1_REG_Q[15]_lut_out, K1_CLK, !H1_TMP, , , , );


--G1_REG_Q[14] is generator_accB:inst4|REG_Q[14]
--operation mode is normal

G1_REG_Q[14]_lut_out = G1L92 & (G1L76 # !G1L34 # !G1L14);
G1_REG_Q[14] = DFFEA(G1_REG_Q[14]_lut_out, K1_CLK, !H1_TMP, , , , );


--L1L51 is VOLTAGE_CONV:inst9|add~8
--operation mode is normal

L1L51_carry_eqn = L1L41;
L1L51 = V1_q_b[7] $ H1_RAMTMP2[7] $ L1L51_carry_eqn;


--P1_CLK is FREDEVIDER2:inst13|CLK
--operation mode is normal

P1_CLK_lut_out = !P1_CLK;
P1_CLK = DFFEA(P1_CLK_lut_out, N1_RD, VCC, , , , );


--S1L5Q is CONV_SINGLE:inst22|CURRENT_STATE~14
--operation mode is normal

S1L5Q_lut_out = S1L5Q & (H1_RAMTMP6[0] # S1L4Q & !S1L63) # !S1L5Q & S1L4Q & !S1L63;
S1L5Q = DFFEA(S1L5Q_lut_out, CLK, VCC, , , , );


--S1L1Q is CONV_SINGLE:inst22|CURRENT_STATE~10
--operation mode is normal

S1L1Q_lut_out = !S1L73 & (H1_RAMTMP6[0] # !S1L24 # !S1L2Q);
S1L1Q = DFFEA(S1L1Q_lut_out, CLK, VCC, , , , );


--S1_EN is CONV_SINGLE:inst22|EN
--operation mode is normal

S1_EN = !S1L5Q & S1L1Q;


--L1L03 is VOLTAGE_CONV:inst9|LessThan~8
--operation mode is normal

L1L03_carry_eqn = L1L82;
L1L03 = L1L51 & V1_q_b[7] & L1L03_carry_eqn # !L1L51 & (V1_q_b[7] # L1L03_carry_eqn);


--L2L51 is VOLTAGE_CONV:inst17|add~8
--operation mode is normal

L2L51_carry_eqn = L2L41;
L2L51 = V2_q_b[7] $ H1_RAMTMP5[7] $ L2L51_carry_eqn;


--L2L03 is VOLTAGE_CONV:inst17|LessThan~8
--operation mode is normal

L2L03_carry_eqn = L2L82;
L2L03 = L2L51 & V2_q_b[7] & L2L03_carry_eqn # !L2L51 & (V2_q_b[7] # L2L03_carry_eqn);


--H1_LATCH_ADDRES[6] is BUS_1:inst5|LATCH_ADDRES[6]
--operation mode is normal

H1_LATCH_ADDRES[6]_lut_out = A1L94;
H1_LATCH_ADDRES[6] = DFFEA(H1_LATCH_ADDRES[6]_lut_out, !ALE, VCC, , , , );


--H1_LATCH_ADDRES[5] is BUS_1:inst5|LATCH_ADDRES[5]
--operation mode is normal

H1_LATCH_ADDRES[5]_lut_out = A1L05;
H1_LATCH_ADDRES[5] = DFFEA(H1_LATCH_ADDRES[5]_lut_out, !ALE, VCC, , , , );


--H1_LATCH_ADDRES[4] is BUS_1:inst5|LATCH_ADDRES[4]
--operation mode is normal

H1_LATCH_ADDRES[4]_lut_out = A1L15;
H1_LATCH_ADDRES[4] = DFFEA(H1_LATCH_ADDRES[4]_lut_out, !ALE, VCC, , , , );


--H1_LATCH_ADDRES[7] is BUS_1:inst5|LATCH_ADDRES[7]
--operation mode is normal

H1_LATCH_ADDRES[7]_lut_out = A1L84;
H1_LATCH_ADDRES[7] = DFFEA(H1_LATCH_ADDRES[7]_lut_out, !ALE, VCC, , , , );


--H1L99 is BUS_1:inst5|reduce_nor~158
--operation mode is normal

H1L99 = H1_LATCH_ADDRES[6] & H1_LATCH_ADDRES[5] & H1_LATCH_ADDRES[4] & H1_LATCH_ADDRES[7];


--H1_LATCH_ADDRES[1] is BUS_1:inst5|LATCH_ADDRES[1]
--operation mode is normal

H1_LATCH_ADDRES[1]_lut_out = A1L45;
H1_LATCH_ADDRES[1] = DFFEA(H1_LATCH_ADDRES[1]_lut_out, !ALE, VCC, , , , );


--H1_LATCH_ADDRES[2] is BUS_1:inst5|LATCH_ADDRES[2]
--operation mode is normal

H1_LATCH_ADDRES[2]_lut_out = A1L35;
H1_LATCH_ADDRES[2] = DFFEA(H1_LATCH_ADDRES[2]_lut_out, !ALE, VCC, , , , );


--H1L001 is BUS_1:inst5|reduce_nor~159
--operation mode is normal

H1L001 = H1L99 & H1_LATCH_ADDRES[1] & !H1_LATCH_ADDRES[2];


--H1_LATCH_ADDRES[0] is BUS_1:inst5|LATCH_ADDRES[0]
--operation mode is normal

H1_LATCH_ADDRES[0]_lut_out = A1L55;
H1_LATCH_ADDRES[0] = DFFEA(H1_LATCH_ADDRES[0]_lut_out, !ALE, VCC, , , , );


--H1_LATCH_ADDRES[3] is BUS_1:inst5|LATCH_ADDRES[3]
--operation mode is normal

H1_LATCH_ADDRES[3]_lut_out = A1L25;
H1_LATCH_ADDRES[3] = DFFEA(H1_LATCH_ADDRES[3]_lut_out, !ALE, VCC, , , , );


--H1L49 is BUS_1:inst5|reduce_nor~3
--operation mode is normal

H1L49 = H1L001 & H1_LATCH_ADDRES[0] & !H1_LATCH_ADDRES[3];


--X1_q_a[1] is BUS_1:inst5|altsyncram:reduce_or_rtl_1|altsyncram_ccj:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
X1_q_a[1]_PORT_A_address = BUS(A1L94, A1L05, A1L15, A1L25, A1L35, A1L45, A1L55, A1L84);
X1_q_a[1]_PORT_A_address_reg = DFFE(X1_q_a[1]_PORT_A_address, X1_q_a[1]_clock_0, , , );
X1_q_a[1]_clock_0 = !ALE;
X1_q_a[1]_PORT_A_data_out = MEMORY(, , X1_q_a[1]_PORT_A_address_reg, , , , , , X1_q_a[1]_clock_0, , , , , );
X1_q_a[1] = X1_q_a[1]_PORT_A_data_out[0];


--H1L92 is BUS_1:inst5|process2~0
--operation mode is normal

H1L92 = !CS & !WR;


--G1L53 is generator_accB:inst4|add~18
--operation mode is arithmetic

G1L53_carry_eqn = G1L43;
G1L53 = G1_REG_Q[17] $ G1L53_carry_eqn;

--G1L63 is generator_accB:inst4|add~18COUT
--operation mode is arithmetic

G1L63 = CARRY(!G1L43 # !G1_REG_Q[17]);


--G1L73 is generator_accB:inst4|add~19
--operation mode is arithmetic

G1L73_carry_eqn = G1L63;
G1L73 = G1_REG_Q[18] $ !G1L73_carry_eqn;

--G1L83 is generator_accB:inst4|add~19COUT
--operation mode is arithmetic

G1L83 = CARRY(G1_REG_Q[18] & !G1L63);


--G1L93 is generator_accB:inst4|add~20
--operation mode is arithmetic

G1L93_carry_eqn = G1L83;
G1L93 = G1_REG_Q[19] $ G1L93_carry_eqn;

--G1L04 is generator_accB:inst4|add~20COUT
--operation mode is arithmetic

G1L04 = CARRY(!G1L83 # !G1_REG_Q[19]);


--G1L76 is generator_accB:inst4|REG_Q~538
--operation mode is normal

G1L76 = !G1L53 & !G1L73 & !G1L93;


--G1L14 is generator_accB:inst4|add~21
--operation mode is arithmetic

G1L14_carry_eqn = G1L04;
G1L14 = G1_REG_Q[20] $ !G1L14_carry_eqn;

--G1L24 is generator_accB:inst4|add~21COUT
--operation mode is arithmetic

G1L24 = CARRY(G1_REG_Q[20] & !G1L04);


--G1L34 is generator_accB:inst4|add~22
--operation mode is normal

G1L34_carry_eqn = G1L24;
G1L34 = G1_REG_Q[21] $ G1L34_carry_eqn;


--G1L07 is generator_accB:inst4|TEMP~0
--operation mode is normal

G1L07 = !H1_TMP & !G1L76 & G1L14 & G1L34;


--L1L31 is VOLTAGE_CONV:inst9|add~7
--operation mode is arithmetic

L1L31_carry_eqn = L1L21;
L1L31 = V1_q_b[6] $ H1_RAMTMP2[6] $ !L1L31_carry_eqn;

--L1L41 is VOLTAGE_CONV:inst9|add~7COUT
--operation mode is arithmetic

L1L41 = CARRY(V1_q_b[6] & (H1_RAMTMP2[6] # !L1L21) # !V1_q_b[6] & H1_RAMTMP2[6] & !L1L21);


--L2L31 is VOLTAGE_CONV:inst17|add~7
--operation mode is arithmetic

L2L31_carry_eqn = L2L21;
L2L31 = V2_q_b[6] $ H1_RAMTMP5[6] $ !L2L31_carry_eqn;

--L2L41 is VOLTAGE_CONV:inst17|add~7COUT
--operation mode is arithmetic

L2L41 = CARRY(V2_q_b[6] & (H1_RAMTMP5[6] # !L2L21) # !V2_q_b[6] & H1_RAMTMP5[6] & !L2L21);


--L1L11 is VOLTAGE_CONV:inst9|add~6
--operation mode is arithmetic

L1L11_carry_eqn = L1L01;
L1L11 = V1_q_b[5] $ H1_RAMTMP2[5] $ L1L11_carry_eqn;

--L1L21 is VOLTAGE_CONV:inst9|add~6COUT
--operation mode is arithmetic

L1L21 = CARRY(V1_q_b[5] & !H1_RAMTMP2[5] & !L1L01 # !V1_q_b[5] & (!L1L01 # !H1_RAMTMP2[5]));


--L2L11 is VOLTAGE_CONV:inst17|add~6
--operation mode is arithmetic

L2L11_carry_eqn = L2L01;
L2L11 = V2_q_b[5] $ H1_RAMTMP5[5] $ L2L11_carry_eqn;

--L2L21 is VOLTAGE_CONV:inst17|add~6COUT
--operation mode is arithmetic

L2L21 = CARRY(V2_q_b[5] & !H1_RAMTMP5[5] & !L2L01 # !V2_q_b[5] & (!L2L01 # !H1_RAMTMP5[5]));


--L1L9 is VOLTAGE_CONV:inst9|add~5
--operation mode is arithmetic

L1L9_carry_eqn = L1L8;
L1L9 = V1_q_b[4] $ H1_RAMTMP2[4] $ !L1L9_carry_eqn;

--L1L01 is VOLTAGE_CONV:inst9|add~5COUT
--operation mode is arithmetic

L1L01 = CARRY(V1_q_b[4] & (H1_RAMTMP2[4] # !L1L8) # !V1_q_b[4] & H1_RAMTMP2[4] & !L1L8);


--L2L9 is VOLTAGE_CONV:inst17|add~5
--operation mode is arithmetic

L2L9_carry_eqn = L2L8;
L2L9 = V2_q_b[4] $ H1_RAMTMP5[4] $ !L2L9_carry_eqn;

--L2L01 is VOLTAGE_CONV:inst17|add~5COUT
--operation mode is arithmetic

L2L01 = CARRY(V2_q_b[4] & (H1_RAMTMP5[4] # !L2L8) # !V2_q_b[4] & H1_RAMTMP5[4] & !L2L8);


--L1L7 is VOLTAGE_CONV:inst9|add~4
--operation mode is arithmetic

L1L7_carry_eqn = L1L6;
L1L7 = V1_q_b[3] $ H1_RAMTMP2[3] $ L1L7_carry_eqn;

--L1L8 is VOLTAGE_CONV:inst9|add~4COUT
--operation mode is arithmetic

L1L8 = CARRY(V1_q_b[3] & !H1_RAMTMP2[3] & !L1L6 # !V1_q_b[3] & (!L1L6 # !H1_RAMTMP2[3]));


--L2L7 is VOLTAGE_CONV:inst17|add~4
--operation mode is arithmetic

L2L7_carry_eqn = L2L6;
L2L7 = V2_q_b[3] $ H1_RAMTMP5[3] $ L2L7_carry_eqn;