alu.v

用verilog编写的32位alu部件

module ALU(A,B,ALUFN,C,RFLAG,WFLAG);//RFLAG为标志寄存器的输出，WFLAG为ALU产生的标志位N,Z,C,O
input[31:0] A,B;
input[3:0] ALUFN;
input[3:0] RFLAG;
output[31:0] C;
output[3:0] WFLAG;
wire[31:0] c_adder,c_logic,c_shift;
wire  N_adder,Z_adder,cf_adder,O_adder,Z_logic,N_logic,cf_shift;
ALU_adder_section(A,B,c_adder,RFLAG[1],ALUFN[1:0],N_adder,Z_adder,cf_adder,O_adder);
//结果影响标志器的N,Z,C,O诸位。
ALU_logic_section(A,B,c_logic,ALUFN[1:0],N_logic,Z_logic);
//结果影响标志器的N,Z诸位,C,O位置零
ALU_shifter_section(B,A[4:0],c_shift,ALUFN[1:0],RFLAG[1],cf_shift);
//仅影响标志器的C位，其他位保持不变
mux4_1_1bit(WFLAG[0],O_adder,RFLAG[0],1'b0,RFLAG[0],ALUFN[3:2]);
mux4_1_1bit(WFLAG[1],cf_adder,RFLAG[1],1'b0,cf_shift,ALUFN[3:2]);
mux4_1_1bit(WFLAG[2],Z_adder,RFLAG[2],Z_logic,RFLAG[2],ALUFN[3:2]);
mux4_1_1bit(WFLAG[3],N_adder,RFLAG[3],N_logic,RFLAG[3],ALUFN[3:2]);
mux4_1_32bit(C,c_adder,B,c_logic,c_shift,ALUFN[3:2]);
endmodule

module ALU_adder_section(a,b,c,c0,functional,N_adder,Z_adder,cf_adder,O_adder);//ALU产生的标志位N,Z,C,O
input[31:0] a,b;
input c0;
input [1:0] functional; //functional ==00 it's add ,==01 it's sub,==10 it's adc,==11 it's sbb
output[31:0] c;
output N_adder,Z_adder,cf_adder,O_adder;
wire c0_in;
reg [31:0] b_in;
always@(functional[0] or b)//二选一
begin 
    case(functional[0]) 
        1'b1: b_in=~b;
        1'b0: b_in=b;
    endcase
end
assign c0_in=(functional[1]||functional[0])&&((~functional[1]&&functional[0])||(c0^functional[0]));                                 
LAC_adder32(a,b_in,c,c0_in,cf_adder,Z_adder);
assign O_adder=(!a[31]&&!b[31]&&c[31])||(a[31]&&b[31]&&!c[31]);
assign N_adder=c[31];
endmodule 

module LAC_adder32(a,b,s,c0,c32,Z);
input[31:0] a,b;
input c0;
output[31:0] s;
reg[31:0] s;
output c32,Z;
wire[15:0] ls,hs1,hs2;
wire c1,c2,c3,ZL,ZH1,ZH2;
LAC_adder16(a[15:0],b[15:0],ls[15:0],c0,c1);
LAC_adder16(a[31:16],b[31:16],hs1[15:0],1'b0,c2);
LAC_adder16(a[31:16],b[31:16],hs2[15:0],1'b1,c3);
always@(hs1 or hs2 or ls or c1)
begin
    if(c1) s={hs2,ls};
    else s={hs1,ls};
end
assign c32=(c1&&c3)||(~c1&&c2);
assign ZL=~(|ls);
assign ZH1=|hs1;
assign ZH2=&hs1;
assign Z=ZL&&((!(ZH1||c1))||(ZH2&&c1));
endmodule

module LAC_adder16(a,b,s,c0,cf);
input[15:0] a,b;
input c0;
output[15:0] s;
output cf;
wire c4,c8,c12,c16;
wire p0,g0,p1,g1,p2,g2,p3,g3;
LAC_adder4(a[3:0],b[3:0],c0,s[3:0],p0,g0);
assign c4=g0||p0&&c0;
LAC_adder4(a[7:4],b[7:4],c4,s[7:4],p1,g1);
assign c8=g1||p1&&g0||p1&&p0&&c0;
LAC_adder4(a[11:8],b[11:8],c8,s[11:8],p2,g2);
assign c12=g2||p2&&g1||p2&&p1&&g0||p2&&p1&&p0&&c0;
LAC_adder4(a[15:12],b[15:12],c12,s[15:12],p3,g3);
assign cf=g3||p3&&g2||p3&&p2&&g1||p3&&p2&&p1&&g0||p3&&p2&&p1&&p0&&c0;
endmodule

module LAC_adder4(a,b,c0,s,outp,outg);
input[3:0] a,b;
input c0;
output[3:0] s;
output outp,outg;
wire c1,c2,c3;
wire[3:0] p,g;
assign g[0]=a[0]&&b[0];
assign g[1]=a[1]&&b[1];
assign g[2]=a[2]&&b[2];
assign g[3]=a[3]&&b[3];
assign p[0]=a[0]^b[0];
assign p[1]=a[1]^b[1];
assign p[2]=a[2]^b[2];
assign p[3]=a[3]^b[3];
assign c1=g[0]||p[0]&&c0;
assign c2=g[1]||(p[1]&&g[0])||(p[1]&&p[0]&&c0);
assign c3=g[2]||(p[2]&&g[1])||(p[2]&&p[1]&&g[0])||(p[2]&&p[1]&&p[0]&&c0);
assign s[0]=p[0]^c0;
assign s[1]=p[1]^c1;
assign s[2]=p[2]^c2;
assign s[3]=p[3]^c3;
assign outp=p[0]&&p[1]&&p[2]&&p[3];
assign outg=g[3]||p[3]&&g[2]||p[3]&&p[2]&&g[1]||p[3]&&p[2]&&p[1]&&g[0];
endmodule

module ALU_logic_section(a,b,c,functional,N_logic,Z_logic);
input[31:0] a,b;
input [1:0] functional;  //functional ==00 it's and ,==01 it's or,==10 it's xor,==11 it's not
output[31:0] c;
output Z_logic,N_logic;
reg[31:0] c;
always@(functional or a or b )
begin 
    case(functional) 
          2'b00: c=a&b;
          2'b01: c=a|b;
          2'b10: c=a^b;
          2'b11: c=~b;
     endcase
end
assign Z_logic=~(|c);
assign N_logic=c[31];
endmodule

module ALU_shifter_section(in,shift_num,out,functional,RC,c32);//RC为原有的进位标志
output [31:0] out;
output c32;
input [31:0] in;
input [4:0] shift_num;
input [1:0] functional;//funtional ＝00  it's SHL,=01  it's SHR,=10  it's SAR,=11 it's ROR
input RC;
reg [31:0] xin,yin,out;
wire[30:0] b;
wire[3:0] cf;
wire [31:0] level1,level2,level3,level4,level5;
assign b[0]=in[0],b[1]=level1[0],b[2]=level1[1],b[3]=level2[0],b[4]=level2[1],b[5]=level2[2],b[6]=level2[3];
assign b[7]=level3[0],b[8]=level3[1],b[9]=level3[2],b[10]=level3[3],b[11]=level3[4],b[12]=level3[5],b[13]=level3[6],b[14]=level3[7];
assign b[15]=level4[0],b[16]=level4[1],b[17]=level4[2],b[18]=level4[3],b[19]=level4[4],b[20]=level4[5],b[21]=level4[6],b[22]=level4[7],b[23]=level4[8],b[24]=level4[9],b[25]=level4[10],b[26]=level4[11],b[27]=level4[12],b[28]=level4[13],b[29]=level4[14],b[30]=level4[15];
always@(in[31] or b or functional)
begin
  case(functional)
	2'b11:yin={1'b0,b};
	2'b10:yin={in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31],in[31]};
	default:yin={32'h00000000};	
  endcase
end
always@(in or functional)
begin
   if(functional==2'b00)
      xin={in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7],in[8],in[9],in[10],in[11],in[12],in[13],in[14],in[15],in[16],in[17],in[18],in[19],in[20],in[21],in[22],in[23],in[24],in[25],in[26],in[27],in[28],in[29],in[30],in[31]};
   else xin=in;   
end
mux2_1 amuxcf(cf[0],RC,xin[0],shift_num[0]);
mux2_1 amux1(level1[0],xin[0],xin[1],shift_num[0]);
mux2_1 amux2(level1[1],xin[1],xin[2],shift_num[0]);
mux2_1 amux3(level1[2],xin[2],xin[3],shift_num[0]);
mux2_1 amux4(level1[3],xin[3],xin[4],shift_num[0]);
mux2_1 amux5(level1[4],xin[4],xin[5],shift_num[0]);
mux2_1 amux6(level1[5],xin[5],xin[6],shift_num[0]);
mux2_1 amux7(level1[6],xin[6],xin[7],shift_num[0]);
mux2_1 amux8(level1[7],xin[7],xin[8],shift_num[0]);
mux2_1 amux9(level1[8],xin[8],xin[9],shift_num[0]);
mux2_1 amux10(level1[9],xin[9],xin[10],shift_num[0]);
mux2_1 amux11(level1[10],xin[10],xin[11],shift_num[0]);
mux2_1 amux12(level1[11],xin[11],xin[12],shift_num[0]);
mux2_1 amux13(level1[12],xin[12],xin[13],shift_num[0]);
mux2_1 amux14(level1[13],xin[13],xin[14],shift_num[0]);
mux2_1 amux15(level1[14],xin[14],xin[15],shift_num[0]);
mux2_1 amux16(level1[15],xin[15],xin[16],shift_num[0]);
mux2_1 amux17(level1[16],xin[16],xin[17],shift_num[0]);
mux2_1 amux18(level1[17],xin[17],xin[18],shift_num[0]);
mux2_1 amux19(level1[18],xin[18],xin[19],shift_num[0]);
mux2_1 amux20(level1[19],xin[19],xin[20],shift_num[0]);
mux2_1 amux21(level1[20],xin[20],xin[21],shift_num[0]);
mux2_1 amux22(level1[21],xin[21],xin[22],shift_num[0]);
mux2_1 amux23(level1[22],xin[22],xin[23],shift_num[0]);
mux2_1 amux24(level1[23],xin[23],xin[24],shift_num[0]);
mux2_1 amux25(level1[24],xin[24],xin[25],shift_num[0]);
mux2_1 amux26(level1[25],xin[25],xin[26],shift_num[0]);
mux2_1 amux27(level1[26],xin[26],xin[27],shift_num[0]);
mux2_1 amux28(level1[27],xin[27],xin[28],shift_num[0]);