clk_1hz.fit.rpt

用verilog实现的记时器程序,在Quartus II上编译通过并成功运行

; Auto Packed Registers -- Stratix II/Cyclone II ; Auto                           ; Auto                           ;
; Auto Delay Chains                              ; On                             ; On                             ;
; Auto Merge PLLs                                ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs              ; Off                            ; Off                            ;
; Fitter Effort                                  ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                ; Normal                         ; Normal                         ;
; Auto Global Clock                              ; On                             ; On                             ;
; Auto Global Register Control Signals           ; On                             ; On                             ;
; Always Enable Input Buffers                    ; Off                            ; Off                            ;
+------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/liao/CLK_1HZ.pin.


+---------------------------------------------------------------------+
; Fitter Resource Usage Summary                                       ;
+---------------------------------------------+-----------------------+
; Resource                                    ; Usage                 ;
+---------------------------------------------+-----------------------+
; Total logic elements                        ; 68 / 33,216 ( < 1 % ) ;
;     -- Combinational with no register       ; 41                    ;
;     -- Register only                        ; 0                     ;
;     -- Combinational with a register        ; 27                    ;
;                                             ;                       ;
; Logic element usage by number of LUT inputs ;                       ;
;     -- 4 input functions                    ; 14                    ;
;     -- 3 input functions                    ; 2                     ;
;     -- <=2 input functions                  ; 52                    ;
;     -- Register only                        ; 0                     ;
;                                             ;                       ;
; Logic elements by mode                      ;                       ;
;     -- normal mode                          ; 43                    ;
;     -- arithmetic mode                      ; 25                    ;
;                                             ;                       ;
; Total registers                             ; 27 / 33,216 ( < 1 % ) ;
; Total LABs                                  ; 5 / 2,076 ( < 1 % )   ;
; User inserted logic elements                ; 0                     ;
; Virtual pins                                ; 0                     ;
; I/O pins                                    ; 2 / 475 ( < 1 % )     ;
;     -- Clock pins                           ; 1 / 8 ( 13 % )        ;
; Global signals                              ; 1                     ;
; M4Ks                                        ; 0 / 105 ( 0 % )       ;
; Total memory bits                           ; 0 / 483,840 ( 0 % )   ;
; Total RAM block bits                        ; 0 / 483,840 ( 0 % )   ;
; Embedded Multiplier 9-bit elements          ; 0 / 70 ( 0 % )        ;
; PLLs                                        ; 0 / 4 ( 0 % )         ;
; Global clocks                               ; 1 / 16 ( 6 % )        ;
; Maximum fan-out node                        ; LessThan0~404         ;
; Maximum fan-out                             ; 27                    ;
; Highest non-global fan-out signal           ; LessThan0~404         ;
; Highest non-global fan-out                  ; 27                    ;
; Total fan-out                               ; 221                   ;
; Average fan-out                             ; 2.19                  ;
+---------------------------------------------+-----------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                 ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clk  ; P2    ; 1        ; 0            ; 18           ; 2           ; 1                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; Fitter               ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                           ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; cout ; U25   ; 6        ; 65           ; 13           ; 1           ; no              ; no                     ; no            ; no              ; no         ; no            ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; Fitter               ; 0 pF ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+


+----------------------------------------------------------+
; I/O Bank Usage                                           ;
+----------+----------------+---------------+--------------+
; I/O Bank ; Usage          ; VCCIO Voltage ; VREF Voltage ;
+----------+----------------+---------------+--------------+
; 1        ; 1 / 64 ( 2 % ) ; 3.3V          ; --           ;
; 2        ; 2 / 59 ( 3 % ) ; 3.3V          ; --           ;
; 3        ; 0 / 56 ( 0 % ) ; 3.3V          ; --           ;
; 4        ; 0 / 58 ( 0 % ) ; 3.3V          ; --           ;
; 5        ; 0 / 65 ( 0 % ) ; 3.3V          ; --           ;
; 6        ; 2 / 59 ( 3 % ) ; 3.3V          ; --           ;
; 7        ; 0 / 58 ( 0 % ) ; 3.3V          ; --           ;
; 8        ; 0 / 56 ( 0 % ) ; 3.3V          ; --           ;
+----------+----------------+---------------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins                                                                                                                                                        ;
+----------+------------+----------+-------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;