clk_1hz.v

来自「用verilog实现的记时器程序,在Quartus II上编译通过并成功运行」· Verilog 代码 · 共 13 行

module CLK_1HZ(clk,cout);
input clk;
output reg cout;
reg [7:0] qs,qf,qm,leds,ledf,ledm;
reg [25:0] q_temp;
always @(posedge clk)
      begin
          if(q_temp<50000000) q_temp=q_temp+1;
          else q_temp=0;
          if(q_temp==0) cout=1;
          else cout=0;
      end
endmodule