jsq24_b.fit.summary

用verilog实现的记时器程序,在Quartus II上编译通过并成功运行

Fitter Status : Successful - Tue Oct 16 21:21:46 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : JSQ24_B
Top-level Entity Name : JSQ24_B
Family : Cyclone II
Device : EP2C35F672C6
Timing Models : Final
Total logic elements : 498 / 33,216 ( 1 % )
Total registers : 51
Total pins : 47 / 475 ( 10 % )
Total virtual pins : 0
Total memory bits : 0 / 483,840 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )