jsq24_b.tan.qmsg

用verilog实现的记时器程序,在Quartus II上编译通过并成功运行

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off JSQ24_B -c JSQ24_B --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off JSQ24_B -c JSQ24_B --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "JM " "Info: Assuming node \"JM\" is an undefined clock" {  } { { "JSQ24_B.bdf" "" { Schematic "G:/zzs/JSQ24_B.bdf" { { 320 -144 24 336 "JM" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "JM" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "JSQ24_B.bdf" "" { Schematic "G:/zzs/JSQ24_B.bdf" { { 56 -112 56 72 "CLK" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "JF " "Info: Assuming node \"JF\" is an undefined clock" {  } { { "JSQ24_B.bdf" "" { Schematic "G:/zzs/JSQ24_B.bdf" { { 376 -128 40 392 "JF" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "JF" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "JS " "Info: Assuming node \"JS\" is an undefined clock" {  } { { "JSQ24_B.bdf" "" { Schematic "G:/zzs/JSQ24_B.bdf" { { 392 -128 40 408 "JS" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "JS" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}