jsq24_b.map.qmsg

用verilog实现的记时器程序,在Quartus II上编译通过并成功运行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 16 21:20:38 2007 " "Info: Processing started: Tue Oct 16 21:20:38 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off JSQ24_B -c JSQ24_B " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off JSQ24_B -c JSQ24_B" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "JSQ24_B.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file JSQ24_B.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 JSQ24_B " "Info: Found entity 1: JSQ24_B" {  } { { "JSQ24_B.bdf" "" { Schematic "G:/zzs/JSQ24_B.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "JSQ24_B " "Info: Elaborating entity \"JSQ24_B\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "dec7s.v 1 1 " "Warning: Using design file dec7s.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 dec7s " "Info: Found entity 1: dec7s" {  } { { "dec7s.v" "" { Text "G:/zzs/dec7s.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dec7s dec7s:inst8 " "Info: Elaborating entity \"dec7s\" for hierarchy \"dec7s:inst8\"" {  } { { "JSQ24_B.bdf" "inst8" { Schematic "G:/zzs/JSQ24_B.bdf" { { 72 304 424 168 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_COMPLICATED_EVENT_EXPR" "CNT60.v(7) " "Warning (10261): Verilog HDL Event Control warning at CNT60.v(7): Event Control contains a complex event expression" {  } { { "CNT60.v" "" { Text "G:/zzs/CNT60.v" 7 0 0 } }  } 0 10261 "Verilog HDL Event Control warning at %1!s!: Event Control contains a complex event expression" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "CNT60.v 1 1 " "Warning: Using design file CNT60.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 CNT60 " "Info: Found entity 1: CNT60" {  } { { "CNT60.v" "" { Text "G:/zzs/CNT60.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CNT60 CNT60:inst1 " "Info: Elaborating entity \"CNT60\" for hierarchy \"CNT60:inst1\"" {  } { { "JSQ24_B.bdf" "inst1" { Schematic "G:/zzs/JSQ24_B.bdf" { { 200 104 200 296 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 CNT60.v(11) " "Warning (10230): Verilog HDL assignment warning at CNT60.v(11): truncated value with size 32 to match size of target (8)" {  } { { "CNT60.v" "" { Text "G:/zzs/CNT60.v" 11 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 CNT60.v(12) " "Warning (10230): Verilog HDL assignment warning at CNT60.v(12): truncated value with size 32 to match size of target (4)" {  } { { "CNT60.v" "" { Text "G:/zzs/CNT60.v" 12 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 CNT60.v(13) " "Warning (10230): Verilog HDL assignment warning at CNT60.v(13): truncated value with size 32 to match size of target (4)" {  } { { "CNT60.v" "" { Text "G:/zzs/CNT60.v" 13 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "CLK_1HZ.v 1 1 " "Warning: Using design file CLK_1HZ.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 CLK_1HZ " "Info: Found entity 1: CLK_1HZ" {  } { { "CLK_1HZ.v" "" { Text "G:/zzs/CLK_1HZ.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CLK_1HZ CLK_1HZ:inst " "Info: Elaborating entity \"CLK_1HZ\" for hierarchy \"CLK_1HZ:inst\"" {  } { { "JSQ24_B.bdf" "inst" { Schematic "G:/zzs/JSQ24_B.bdf" { { 32 104 200 128 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 26 CLK_1HZ.v(8) " "Warning (10230): Verilog HDL assignment warning at CLK_1HZ.v(8): truncated value with size 32 to match size of target (26)" {  } { { "CLK_1HZ.v" "" { Text "G:/zzs/CLK_1HZ.v" 8 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_COMPLICATED_EVENT_EXPR" "CNT24.v(7) " "Warning (10261): Verilog HDL Event Control warning at CNT24.v(7): Event Control contains a complex event expression" {  } { { "CNT24.v" "" { Text "G:/zzs/CNT24.v" 7 0 0 } }  } 0 10261 "Verilog HDL Event Control warning at %1!s!: Event Control contains a complex event expression" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "CNT24.v 1 1 " "Warning: Using design file CNT24.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 CNT24 " "Info: Found entity 1: CNT24" {  } { { "CNT24.v" "" { Text "G:/zzs/CNT24.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CNT24 CNT24:inst3 " "Info: Elaborating entity \"CNT24\" for hierarchy \"CNT24:inst3\"" {  } { { "JSQ24_B.bdf" "inst3" { Schematic "G:/zzs/JSQ24_B.bdf" { { 200 440 536 296 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 CNT24.v(11) " "Warning (10230): Verilog HDL assignment warning at CNT24.v(11): truncated value with size 32 to match size of target (8)" {  } { { "CNT24.v" "" { Text "G:/zzs/CNT24.v" 11 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 CNT24.v(12) " "Warning (10230): Verilog HDL assignment warning at CNT24.v(12): truncated value with size 32 to match size of target (4)" {  } { { "CNT24.v" "" { Text "G:/zzs/CNT24.v" 12 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 CNT24.v(13) " "Warning (10230): Verilog HDL assignment warning at CNT24.v(13): truncated value with size 32 to match size of target (4)" {  } { { "CNT24.v" "" { Text "G:/zzs/CNT24.v" 13 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/lpm_divide.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_divide.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide " "Info: Found entity 1: lpm_divide" {  } { { "lpm_divide.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_divide.tdf" 116 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "CNT60:inst1\|lpm_divide:Mod0 " "Info: Elaborated megafunction instantiation \"CNT60:inst1\|lpm_divide:Mod0\"" {  } { { "CNT60.v" "" { Text "G:/zzs/CNT60.v" 13 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_45m.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_45m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_45m " "Info: Found entity 1: lpm_divide_45m" {  } { { "db/lpm_divide_45m.tdf" "" { Text "G:/zzs/db/lpm_divide_45m.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_bkh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_bkh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_bkh " "Info: Found entity 1: sign_div_unsign_bkh" {  } { { "db/sign_div_unsign_bkh.tdf" "" { Text "G:/zzs/db/sign_div_unsign_bkh.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_ove.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_ove.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_ove " "Info: Found entity 1: alt_u_div_ove" {  } { { "db/alt_u_div_ove.tdf" "" { Text "G:/zzs/db/alt_u_div_ove.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_lkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_lkc " "Info: Found entity 1: add_sub_lkc" {  } { { "db/add_sub_lkc.tdf" "" { Text "G:/zzs/db/add_sub_lkc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_mkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_mkc " "Info: Found entity 1: add_sub_mkc" {  } { { "db/add_sub_mkc.tdf" "" { Text "G:/zzs/db/add_sub_mkc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "CNT60:inst1\|lpm_divide:Div0 " "Info: Elaborated megafunction instantiation \"CNT60:inst1\|lpm_divide:Div0\"" {  } { { "CNT60.v" "" { Text "G:/zzs/CNT60.v" 12 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_1dm.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_1dm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_1dm " "Info: Found entity 1: lpm_divide_1dm" {  } { { "db/lpm_divide_1dm.tdf" "" { Text "G:/zzs/db/lpm_divide_1dm.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "569 " "Info: Implemented 569 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "42 " "Info: Implemented 42 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "522 " "Info: Implemented 522 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 16 21:21:16 2007 " "Info: Processing ended: Tue Oct 16 21:21:16 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:39 " "Info: Elapsed time: 00:00:39" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}