jsq24_v.v

来自「用verilog实现的记时器程序,在Quartus II上编译通过并成功运行」· Verilog 代码 · 共 17 行

module JSQ24_V(CLK,CLR,JM,JF,JS,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,COUT);
input CLK,CLR,JM,JF,JS;
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5;
output COUT;
wire [7:0] QM,QF,QS;
wire [7:0] X1,X2,X3;
CLK_1HZ U1(CLK,X1);
CNT60   U2(X1,JM,CLR,QM,X2);
CNT60   U3(X2,JF,CLR,QF,X3);
CNT24   U4(X3,JS,CLR,QS,COUT);
dec7s   U5(QM[3:0],HEX0[6:0]);
dec7s   U6(QM[7:4],HEX1[6:0]);
dec7s   U7(QF[3:0],HEX2[6:0]);
dec7s   U8(QF[7:4],HEX3[6:0]);
dec7s   U9(QS[3:0],HEX4[6:0]);
dec7s   U10(QS[7:4],HEX5[6:0]);
endmodule