dec_8421.tan.qmsg

用verilog实现的记时器程序,在Quartus II上编译通过并成功运行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 09 20:45:24 2007 " "Info: Processing started: Tue Oct 09 20:45:24 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off dec_8421 -c dec_8421 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dec_8421 -c dec_8421 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[3\] hex\[3\] 10.023 ns Longest " "Info: Longest tpd from source pin \"a\[3\]\" to destination pin \"hex\[3\]\" is 10.023 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.840 ns) 0.840 ns a\[3\] 1 PIN PIN_D16 7 " "Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_D16; Fanout = 7; PIN Node = 'a\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { a[3] } "NODE_NAME" } } { "dec_8421.v" "" { Text "E:/LIAO/dec_8421/dec_8421.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.090 ns) + CELL(0.275 ns) 6.205 ns WideOr3~4 2 COMB LCCOMB_X36_Y35_N10 1 " "Info: 2: + IC(5.090 ns) + CELL(0.275 ns) = 6.205 ns; Loc. = LCCOMB_X36_Y35_N10; Fanout = 1; COMB Node = 'WideOr3~4'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.365 ns" { a[3] WideOr3~4 } "NODE_NAME" } } { "dec_8421.v" "" { Text "E:/LIAO/dec_8421/dec_8421.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(2.788 ns) 10.023 ns hex\[3\] 3 PIN PIN_C12 0 " "Info: 3: + IC(1.030 ns) + CELL(2.788 ns) = 10.023 ns; Loc. = PIN_C12; Fanout = 0; PIN Node = 'hex\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.818 ns" { WideOr3~4 hex[3] } "NODE_NAME" } } { "dec_8421.v" "" { Text "E:/LIAO/dec_8421/dec_8421.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.903 ns ( 38.94 % ) " "Info: Total cell delay = 3.903 ns ( 38.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.120 ns ( 61.06 % ) " "Info: Total interconnect delay = 6.120 ns ( 61.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.023 ns" { a[3] WideOr3~4 hex[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.023 ns" { a[3] a[3]~combout WideOr3~4 hex[3] } { 0.000ns 0.000ns 5.090ns 1.030ns } { 0.000ns 0.840ns 0.275ns 2.788ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 09 20:45:24 2007 " "Info: Processing ended: Tue Oct 09 20:45:24 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}