dec_8421.v

用verilog实现的记时器程序,在Quartus II上编译通过并成功运行

module dec_8421(a,hex);
    input[3:0]  a;
    output reg[6:0] hex;
always @(a)
  begin
  case (a)
       0 : hex = 'b1000000;
       1 : hex = 'b1111001;
       2 : hex = 'b0100100;
       3 : hex = 'b0110000;
	   4 : hex = 'b0011001;
	   5 : hex = 'b0010010;
	   6 : hex = 'b0000010;
	   7 : hex = 'b1111000;
	   8 : hex = 'b0000000;
	   9 : hex = 'b0010000;
	  10 : hex = 'b0001000;
	  11 : hex = 'b0000011;
	  12 : hex = 'b1000110;
	  13 : hex = 'b0100001;
	  14 : hex = 'b0000110;
	  15 : hex = 'b0001110;
	endcase
end 
endmodule