cnt24.v

来自「用verilog实现的记时器程序,在Quartus II上编译通过并成功运行」· Verilog 代码 · 共 20 行

module CNT24(clk,js,clr,Q,cout);
input clk,js,clr;
output reg [7:0] Q;
output cout;
reg cout;
reg [7:0] q_temp;
always @(negedge clr or posedge (clk^^js))
   begin
     if (~clr) q_temp=0;
     else if(q_temp==23) q_temp=0;
          else q_temp=q_temp+1;
          Q[7:4]=q_temp/10;
          Q[3:0]=q_temp%10;
   end
always
   begin
     if(q_temp==23) cout=0;
     else cout=1;
   end
endmodule