cnt60.tan.summary

来自「用verilog实现的记时器程序,在Quartus II上编译通过并成功运行」· SUMMARY 代码 · 共 47 行

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 21.086 ns
From           : q_temp[5]
To             : Q[4]
From Clock     : js
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'js'
Slack          : N/A
Required Time  : None
Actual Time    : 407.50 MHz ( period = 2.454 ns )
From           : q_temp[0]
To             : q_temp[4]
From Clock     : js
To Clock       : js
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 407.50 MHz ( period = 2.454 ns )
From           : q_temp[0]
To             : q_temp[4]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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