dec7s.v

来自「用verilog实现的记时器程序,在Quartus II上编译通过并成功运行」· Verilog 代码 · 共 27 行

module dec7s(a,q);
input [3:0] a;
output [6:0] q;
reg [6:0] q;
always @(a)
   begin
      case(a)
           0: q=7'b1000000;
           1: q=7'b1111001;
           2: q=7'b0100100;
           3: q=7'b0110000;
           4: q=7'b0011001;
           5: q=7'b0010010;
           6: q=7'b0000010;
           7: q=7'b1111000;
           8: q=7'b0000000;
           9: q=7'b0010000;
           10: q=7'b0001000;
           11: q=7'b0000011;
           12: q=7'b1000110;
           13: q=7'b0100001;
           14: q=7'b0000110;
           15: q=7'b0001110;
       default :q=7'b1111111;
      endcase
    end
endmodule