jsq24_v.map.summary

用verilog实现的记时器程序,在Quartus II上编译通过并成功运行

Analysis & Synthesis Status : Successful - Tue Oct 16 18:42:33 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : JSQ24_V
Top-level Entity Name : JSQ24_V
Family : Cyclone II
Total logic elements : 499
Total registers : 51
Total pins : 48
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0