prev_cmp_dianzirili.qmsg

用verilog实现的电子日历程序,在Quartus II上编译通过并成功实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 26 00:14:18 2007 " "Info: Processing started: Fri Oct 26 00:14:18 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dianzirili -c dianzirili " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dianzirili -c dianzirili" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "dianzirili.v(126) " "Warning (10268): Verilog HDL information at dianzirili.v(126): Always Construct contains both blocking and non-blocking assignments" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 126 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "dianzirili.v(143) " "Warning (10268): Verilog HDL information at dianzirili.v(143): Always Construct contains both blocking and non-blocking assignments" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 143 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "dianzirili.v(157) " "Warning (10268): Verilog HDL information at dianzirili.v(157): Always Construct contains both blocking and non-blocking assignments" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 157 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "dianzirili.v(171) " "Warning (10268): Verilog HDL information at dianzirili.v(171): Always Construct contains both blocking and non-blocking assignments" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 171 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "dianzirili.v(204) " "Warning (10268): Verilog HDL information at dianzirili.v(204): Always Construct contains both blocking and non-blocking assignments" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 204 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "dianzirili.v(218) " "Warning (10268): Verilog HDL information at dianzirili.v(218): Always Construct contains both blocking and non-blocking assignments" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 218 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "dianzirili.v(230) " "Warning (10268): Verilog HDL information at dianzirili.v(230): Always Construct contains both blocking and non-blocking assignments" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 230 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dianzirili.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dianzirili.v" { { "Info" "ISGN_ENTITY_NAME" "1 dianzirili " "Info: Found entity 1: dianzirili" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dianzirili " "Info: Elaborating entity \"dianzirili\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "alert1 dianzirili.v(39) " "Warning (10858): Verilog HDL warning at dianzirili.v(39): object alert1 used but never assigned" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 39 0 0 } }  } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 dianzirili.v(47) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(47): truncated value with size 32 to match size of target (2)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 47 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 dianzirili.v(54) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(54): truncated value with size 32 to match size of target (3)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 54 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "count1 dianzirili.v(81) " "Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(81): inferring latch(es) for variable \"count1\", which holds its previous value in one or more paths through the always construct" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 81 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "count2 dianzirili.v(81) " "Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(81): inferring latch(es) for variable \"count2\", which holds its previous value in one or more paths through the always construct" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 81 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "count3 dianzirili.v(81) " "Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(81): inferring latch(es) for variable \"count3\", which holds its previous value in one or more paths through the always construct" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 81 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "count4 dianzirili.v(81) " "Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(81): inferring latch(es) for variable \"count4\", which holds its previous value in one or more paths through the always construct" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 81 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "LD_min dianzirili.v(81) " "Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(81): inferring latch(es) for variable \"LD_min\", which holds its previous value in one or more paths through the always construct" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 81 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "LD_hour dianzirili.v(81) " "Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(81): inferring latch(es) for variable \"LD_hour\", which holds its previous value in one or more paths through the always construct" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 81 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "LD_mon dianzirili.v(81) " "Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(81): inferring latch(es) for variable \"LD_mon\", which holds its previous value in one or more paths through the always construct" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 81 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "LD_day dianzirili.v(81) " "Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(81): inferring latch(es) for variable \"LD_day\", which holds its previous value in one or more paths through the always construct" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 81 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "LD_week dianzirili.v(81) " "Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(81): inferring latch(es) for variable \"LD_week\", which holds its previous value in one or more paths through the always construct" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 81 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 dianzirili.v(87) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(87): truncated value with size 32 to match size of target (2)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 87 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 dianzirili.v(94) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(94): truncated value with size 32 to match size of target (2)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 94 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 dianzirili.v(101) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(101): truncated value with size 32 to match size of target (2)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 101 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 dianzirili.v(108) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(108): truncated value with size 32 to match size of target (2)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 108 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 dianzirili.v(115) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(115): truncated value with size 32 to match size of target (2)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 115 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 dianzirili.v(119) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(119): truncated value with size 2 to match size of target (1)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 119 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 dianzirili.v(120) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(120): truncated value with size 2 to match size of target (1)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 120 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}