dianzirili.fit.summary

来自「用verilog实现的电子日历程序,在Quartus II上编译通过并成功实现」· SUMMARY 代码 · 共 18 行

Fitter Status : Successful - Fri Oct 26 00:14:45 2007
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : dianzirili
Top-level Entity Name : dianzirili
Family : Stratix II
Device : EP2S15F484C3
Timing Models : Final
Logic utilization : 2 %
    Combinational ALUTs : 192 / 12,480 ( 2 % )
    Dedicated logic registers : 70 / 12,480 ( < 1 % )
Total registers : 70
Total pins : 40 / 343 ( 12 % )
Total virtual pins : 0
Total block memory bits : 0 / 419,328 ( 0 % )
DSP block 9-bit elements : 0 / 96 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )