prev_cmp_dianzirili.map.qmsg

用verilog实现的电子日历程序,在Quartus II上编译通过并成功实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 26 00:13:45 2007 " "Info: Processing started: Fri Oct 26 00:13:45 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dianzirili -c dianzirili " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dianzirili -c dianzirili" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "dianzirili.v(126) " "Warning (10268): Verilog HDL information at dianzirili.v(126): Always Construct contains both blocking and non-blocking assignments" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 126 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "dianzirili.v(143) " "Warning (10268): Verilog HDL information at dianzirili.v(143): Always Construct contains both blocking and non-blocking assignments" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 143 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "dianzirili.v(157) " "Warning (10268): Verilog HDL information at dianzirili.v(157): Always Construct contains both blocking and non-blocking assignments" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 157 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "dianzirili.v(171) " "Warning (10268): Verilog HDL information at dianzirili.v(171): Always Construct contains both blocking and non-blocking assignments" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 171 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "dianzirili.v(204) " "Warning (10268): Verilog HDL information at dianzirili.v(204): Always Construct contains both blocking and non-blocking assignments" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 204 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "dianzirili.v(218) " "Warning (10268): Verilog HDL information at dianzirili.v(218): Always Construct contains both blocking and non-blocking assignments" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 218 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "dianzirili.v(230) " "Warning (10268): Verilog HDL information at dianzirili.v(230): Always Construct contains both blocking and non-blocking assignments" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 230 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dianzirili.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dianzirili.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Error" "ESGN_TOP_ENTITY_IS_MISSING" "dianzirili " "Error: Top-level design entity \"dianzirili\" is undefined" {  } {  } 0 0 "Top-level design entity \"%1!s!\" is undefined" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/zzs4/dianzirili.map.smsg " "Info: Generated suppressed messages file E:/zzs4/dianzirili.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "131 " "Info: Allocated 131 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Fri Oct 26 00:13:47 2007 " "Error: Processing ended: Fri Oct 26 00:13:47 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}