dianzirili.tan.summary

用verilog实现的电子日历程序,在Quartus II上编译通过并成功实现

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.251 ns
From           : change
To             : loop5[1]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 19.973 ns
From           : min1[0]
To             : alert
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 7.550 ns
From           : clk_1k
To             : alert
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 8.454 ns
From           : turn
To             : sec1[0]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 88.48 MHz ( period = 11.302 ns )
From           : sec1[5]
To             : minclk
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'turn'
Slack          : N/A
Required Time  : None
Actual Time    : 109.71 MHz ( period = 9.115 ns )
From           : min1[2]
To             : hclk
From Clock     : turn
To Clock       : turn
Failed Paths   : 0

Type           : Clock Setup: 'mode'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 500.00 MHz ( period = 2.000 ns )
From           : m[1]
To             : m[0]
From Clock     : mode
To Clock       : mode
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : mon1[2]
To             : mon1[3]
From Clock     : clk
To Clock       : clk
Failed Paths   : 207

Type           : Clock Hold: 'mode'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : m[2]
To             : min[0]$latch
From Clock     : mode
To Clock       : mode
Failed Paths   : 81

Type           : Clock Hold: 'turn'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : mon1[2]
To             : mon1[3]
From Clock     : turn
To Clock       : turn
Failed Paths   : 33

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 321

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