dianzirili.map.summary

用verilog实现的电子日历程序,在Quartus II上编译通过并成功实现

Analysis & Synthesis Status : Successful - Fri Oct 26 00:14:22 2007
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : dianzirili
Top-level Entity Name : dianzirili
Family : Stratix II
Logic utilization : N/A
    Combinational ALUTs : 192
    Dedicated logic registers : 70
Total registers : 70
Total pins : 40
Total virtual pins : 0
Total block memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0