📄 __projnav.log
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ISE Auto-Make Log File-----------------------
Starting: 'jhdparse @_clock.jp'
JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc. All rights reserved.
Scanning d:/Xilinx_WebPACK/data/simprim.lst
Scanning d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
Scanning clock.v
Writing clock.jhd.
JHDPARSE complete - 0 errors, 0 warnings.
Done: completed successfully.
ISE Auto-Make Log File-----------------------
Updating: Assign Pins (ChipViewer)
Starting: 'exewrap @__clock_2prj_exewrap.rsp'
Creating TCL ProcessDone: completed successfully.
Starting: 'exewrap -mode pipe -tapkeep -command D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn clock.xst -ofn clock.syr'
Starting: 'D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn clock.xst -ofn clock.syr 'Release 4.1WP3.x - xst E.33Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.--> Parameter TMPDIR set to .CPU : 0.00 / 0.22 s | Elapsed : 0.00 / 0.00 s --> Parameter overwrite set to YESCPU : 0.00 / 0.22 s | Elapsed : 0.00 / 0.00 s --> =========================================================================---- Source ParametersInput Format : VERILOGInput File Name : clock.prj---- Target ParametersTarget Device : XC9500Output File Name : clockOutput Format : NGCTarget Technology : 9500---- Source OptionsTop Module Name : clockAutomatic FSM Extraction : YESFSM Encoding Algorithm : AutoFSM Flip-Flop Type : DMux Extraction : YESResource Sharing : YESComplex Clock Enable Extraction : YES---- Target OptionsAdd IO Buffers : YESEquivalent register Removal : YESMacro Generator : AutoMACRO Preserve : YESXOR Preserve : YES---- General OptionsOptimization Criterion : SpeedOptimization Effort : 1Check Attribute Syntax : YESKeep Hierarchy : YES---- Other Optionswysiwyg : NO========================================================================= Compiling source file : clock.prjCompiling included source file 'clock.v'Module <clock> compiled.Continuing compilation of source file 'clock.prj'Compiling included source file 'd:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v'Continuing compilation of source file 'clock.prj'No errors in compilationAnalysis of file <clock.prj> succeeded. Starting Verilog synthesis. Analyzing top module <clock>.WARNING:Xst:854 - "clock.v", line 12: Ignored initial statement.WARNING:Xst:905 - "clock.v", line 30: The signals <sec> are missing in the sensitivity list of always block.WARNING:Xst:905 - "clock.v", line 36: The signals <min> are missing in the sensitivity list of always block.WARNING:Xst:905 - "clock.v", line 46: The signals <count, sec> are missing in the sensitivity list of always block.Module <clock> is correct for synthesis.Synthesizing Unit <clock>. Related source file is clock.v.WARNING:Xst:737 - Found 1-bit latch for signal <keyen_reg>. Found 16x8-bit ROM for internal node. Found 4-bit adder for signal <$n0000> created at line 85. Found 4-bit adder for signal <$n0001> created at line 89. Found 4-bit adder for signal <$n0002> created at line 93. Found 4-bit adder for signal <$n0003> created at line 97. Found 23-bit adder for signal <$old_count_1>. Found 23-bit register for signal <count>. Found 4-bit 4-to-1 multiplexer for signal <ledbuf>. Found 16-bit register for signal <min>. Found 1-bit register for signal <sec>. Found 8 1-bit 2-to-1 multiplexers. Summary: inferred 1 ROM(s). inferred 40 D-type flip-flop(s). inferred 1 Latch(s). inferred 5 Adder/Subtracter(s). inferred 12 Multiplexer(s).Unit <clock> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# ROMs : 1 16x8-bit ROM : 1# Registers : 18 23-bit register : 1 1-bit register : 17# Latches : 1 1-bit latch : 1# Multiplexers : 2 4-bit 4-to-1 multiplexer : 1 2-to-1 multiplexer : 1# Adders/Subtractors : 5 4-bit adder : 4 23-bit adder : 1=========================================================================Starting low level synthesis...Optimizing unit <clock> ...=========================================================================Final ResultsOutput File Name : clockOutput Format : NGCOptimization Criterion : SpeedTarget Technology : 9500Keep Hierarchy : YESMacro Preserve : YESMacro Generation : AutoXOR Preserve : YESMacro Statistics# Xors : 34 1-bit xor2 : 34Design Statistics# Edif Instances : 362# I/Os : 15=========================================================================CPU : 3.63 / 3.85 s | Elapsed : 3.00 / 3.00 s --> EXEWRAP detected that program 'D:/Xilinx_WebPACK/bin/nt/xst.exe' completed successfully.Done: completed successfully.
Starting: 'exewrap -tapkeep -mode pipe -tcl -command d:/Xilinx_WebPACK/data/projnav/_edfTOngd.tcl _ngdbld.rsp clock ngdbuild.rsp'
Creating TCL ProcessStarting: 'ngdbuild -f ngdbuild.rsp'Release 4.1WP3.x - ngdbuild E.33Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc clock.ucf -p XC9500 clock.ngc clock.ngd Reading NGO file "F:/ /Xilinx/clock/clock.ngc" ...Reading component libraries for design expansion...Running LogiBLOX expansion on symbol "Madd__n0000_Mxor_Result_1"...WARNING:LBEngine:353 - Module Madd__n0000_Mxor_Result_1 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0000_Mxor_Result_2"...WARNING:LBEngine:353 - Module Madd__n0000_Mxor_Result_2 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0000_Mxor_Result_3"...WARNING:LBEngine:353 - Module Madd__n0000_Mxor_Result_3 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0001_Mxor_Result_1"...WARNING:LBEngine:353 - Module Madd__n0001_Mxor_Result_1 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0001_Mxor_Result_2"...WARNING:LBEngine:353 - Module Madd__n0001_Mxor_Result_2 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0001_Mxor_Result_3"...WARNING:LBEngine:353 - Module Madd__n0001_Mxor_Result_3 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0002_Mxor_Result_1"...WARNING:LBEngine:353 - Module Madd__n0002_Mxor_Result_1 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0002_Mxor_Result_2"...WARNING:LBEngine:353 - Module Madd__n0002_Mxor_Result_2 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0002_Mxor_Result_3"...WARNING:LBEngine:353 - Module Madd__n0002_Mxor_Result_3 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0003_Mxor_Result_1"...WARNING:LBEngine:353 - Module Madd__n0003_Mxor_Result_1 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0003_Mxor_Result_2"...WARNING:LBEngine:353 - Module Madd__n0003_Mxor_Result_2 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0003_Mxor_Result_3"...WARNING:LBEngine:353 - Module Madd__n0003_Mxor_Result_3 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_1"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_1 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_10"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_10 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_11"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_11 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_12"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_12 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_13"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_13 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_14"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_14 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_15"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_15 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_16"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_16 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_17"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_17 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_18"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_18 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_19"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_19 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_2"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_2 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_20"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_20 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_21"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_21 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_22"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_22 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_3"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_3 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_4"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_4 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_5"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_5 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_6"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_6 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_7"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_7 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_8"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_8 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_9"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_9 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Annotating constraints to design from file "clock.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "clock.ngd" ...Writing NGDBUILD log file "clock.bld"...NGDBUILD done.Tcl d:/Xilinx_WebPACK/data/projnav/_edfTOngd.tcl detected that program 'ngdbuild -f ngdbuild.rsp' completed successfully.Done: completed successfully.
Starting: 'exewrap -mode pipe -tapkeep -tcl -command _chipview.tcl'
Creating TCL ProcessStarting: 'ChipView.bat -f clock.ngd -uc clock.ucf -dev XC95108-7-PC84'Tcl _chipview.tcl detected that program 'ChipView.bat -f clock.ngd -uc clock.ucf -dev XC95108-7-PC84' completed successfully.Starting: 'chkdate'Tcl _chipview.tcl detected that program 'chkdate' completed successfully.Existing implementation results (if any) will be retained.Done: completed successfully.
ISE Auto-Make Log File-----------------------
Starting: 'jhdparse @_clock.jp'
JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc. All rights reserved.
Scanning d:/Xilinx_WebPACK/data/simprim.lst
Scanning d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
Scanning clock.v
Writing clock.jhd.
JHDPARSE complete - 0 errors, 0 warnings.
Done: completed successfully.
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