📄 cnt100.rpt
字号:
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 8/ 96( 8%) 5/ 48( 10%) 0/ 48( 0%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\0zht\c2\cnt100.rpt
cnt100
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 clk
Device-Specific Information: d:\0zht\c2\cnt100.rpt
cnt100
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 9 rst
Device-Specific Information: d:\0zht\c2\cnt100.rpt
cnt100
** EQUATIONS **
ce : INPUT;
clk : INPUT;
rst : INPUT;
-- Node name is ':21' = 'c'
-- Equation name is 'c', location is LC6_B7, type is buried.
c = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, !_LC1_B7);
_EQ001 = ce & _LC6_B1
# c & !ce;
-- Node name is 'ca'
-- Equation name is 'ca', type is output
ca = c;
-- Node name is 'co10'
-- Equation name is 'co10', type is output
co10 = s10;
-- Node name is 'co11'
-- Equation name is 'co11', type is output
co11 = s11;
-- Node name is 'co12'
-- Equation name is 'co12', type is output
co12 = s12;
-- Node name is 'co13'
-- Equation name is 'co13', type is output
co13 = s13;
-- Node name is 'co20'
-- Equation name is 'co20', type is output
co20 = s20;
-- Node name is 'co21'
-- Equation name is 'co21', type is output
co21 = s21;
-- Node name is 'co22'
-- Equation name is 'co22', type is output
co22 = s22;
-- Node name is 'co23'
-- Equation name is 'co23', type is output
co23 = s23;
-- Node name is 'rst~1'
-- Equation name is 'rst~1', location is LC1_B7, type is buried.
-- synthesized logic cell
!_LC1_B7 = _LC1_B7~NOT;
_LC1_B7~NOT = LCELL(!rst);
-- Node name is ':16' = 's10'
-- Equation name is 's10', location is LC1_B11, type is buried.
s10 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!rst), VCC, VCC);
_EQ002 = !ce & s10
# ce & !s10;
-- Node name is ':15' = 's11'
-- Equation name is 's11', location is LC8_B11, type is buried.
s11 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!rst), VCC, VCC);
_EQ003 = !_LC4_B11 & !s10 & s11
# ce & !_LC4_B11 & s10 & !s11
# !ce & s11;
-- Node name is ':14' = 's12'
-- Equation name is 's12', location is LC5_B11, type is buried.
s12 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!rst), VCC, VCC);
_EQ004 = !_LC3_B11 & !_LC4_B11 & s12
# ce & _LC3_B11 & !_LC4_B11 & !s12
# !ce & s12;
-- Node name is ':13' = 's13'
-- Equation name is 's13', location is LC2_B11, type is buried.
s13 = DFFE( _EQ005, GLOBAL( clk), GLOBAL(!rst), VCC, VCC);
_EQ005 = ce & !_LC4_B11 & _LC6_B11
# !ce & s13;
-- Node name is ':20' = 's20'
-- Equation name is 's20', location is LC7_B11, type is buried.
s20 = DFFE( _EQ006, GLOBAL( clk), GLOBAL(!rst), VCC, VCC);
_EQ006 = !_LC4_B11 & !_LC6_B1 & s20
# ce & _LC4_B11 & !_LC6_B1 & !s20
# !ce & s20;
-- Node name is ':19' = 's21'
-- Equation name is 's21', location is LC4_B1, type is buried.
s21 = DFFE( _EQ007, GLOBAL( clk), GLOBAL(!rst), VCC, VCC);
_EQ007 = ce & _LC5_B1 & !_LC6_B1
# !ce & s21;
-- Node name is ':18' = 's22'
-- Equation name is 's22', location is LC1_B1, type is buried.
s22 = DFFE( _EQ008, GLOBAL( clk), GLOBAL(!rst), VCC, VCC);
_EQ008 = ce & !_LC6_B1 & _LC7_B1
# !ce & s22;
-- Node name is ':17' = 's23'
-- Equation name is 's23', location is LC3_B1, type is buried.
s23 = DFFE( _EQ009, GLOBAL( clk), GLOBAL(!rst), VCC, VCC);
_EQ009 = ce & !_LC6_B1 & _LC8_B1
# !ce & s23;
-- Node name is '|LPM_ADD_SUB:153|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B4', type is buried
_LC2_B4 = LCELL( _EQ010);
_EQ010 = s20 & s21;
-- Node name is '|LPM_ADD_SUB:180|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B11', type is buried
_LC3_B11 = LCELL( _EQ011);
_EQ011 = s10 & s11;
-- Node name is '|LPM_ADD_SUB:180|addcore:adder|:69' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC6_B11', type is buried
_LC6_B11 = LCELL( _EQ012);
_EQ012 = !s11 & s13
# !s10 & s13
# !s12 & s13
# s10 & s11 & s12 & !s13;
-- Node name is '~109~1'
-- Equation name is '~109~1', location is LC2_B1, type is buried.
-- synthesized logic cell
!_LC2_B1 = _LC2_B1~NOT;
_LC2_B1~NOT = LCELL( _EQ013);
_EQ013 = !s23
# s22
# s21;
-- Node name is ':109'
-- Equation name is '_LC6_B1', type is buried
!_LC6_B1 = _LC6_B1~NOT;
_LC6_B1~NOT = LCELL( _EQ014);
_EQ014 = !s20
# !_LC2_B1
# !_LC4_B11;
-- Node name is ':114'
-- Equation name is '_LC4_B11', type is buried
_LC4_B11 = LCELL( _EQ015);
_EQ015 = s10 & !s11 & !s12 & s13;
-- Node name is ':239'
-- Equation name is '_LC8_B1', type is buried
_LC8_B1 = LCELL( _EQ016);
_EQ016 = !_LC2_B4 & s23
# !s22 & s23
# _LC2_B4 & _LC4_B11 & s22 & !s23
# !_LC4_B11 & s23;
-- Node name is ':248'
-- Equation name is '_LC7_B1', type is buried
_LC7_B1 = LCELL( _EQ017);
_EQ017 = !s21 & s22
# !s20 & s22
# _LC4_B11 & s20 & s21 & !s22
# !_LC4_B11 & s22;
-- Node name is ':257'
-- Equation name is '_LC5_B1', type is buried
_LC5_B1 = LCELL( _EQ018);
_EQ018 = !s20 & s21
# _LC4_B11 & s20 & !s21
# !_LC4_B11 & s21;
Project Information d:\0zht\c2\cnt100.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 20,919K
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