ad.vhd

功能更加完善的基于vhdl的数字时钟设计 有秒表

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ad is 
  port(eoc,clk:in std_logic;
         din: in std_logic_vector(7 downto 0);
         ale,str,oe :out std_logic;
         dout:out std_logic_vector(7 downto 0));
end ad;
architecture behav of ad is 
      type states is(st0,st1,st2,st3,st4,st5,st6,st7);
      signal currentst,nextst:states:=st0;
      signal regl:std_logic_vector(7 downto 0);
      signal lock:std_logic;
      begin
         reg:process(clk)
            begin
            if rising_edge(clk) then 
               currentst<=nextst;
            end if;
        end process reg;
        com:process(currentst,eoc)
            begin
            case currentst is 
               when st0 => ale<='0';str<='0';oe<='0';lock<='0';
                   nextst<=st1;
               when st1 => ale<='1';str<='0';oe<='0';lock<='0';
                   nextst<=st2;
               when st2 => ale<='1';str<='1';oe<='0';lock<='0';
                   nextst<=st3;
               when st3 => ale<='1';str<='1';oe<='0';lock<='0';
                   if eoc='0' then
                   nextst<=st4;
                   else
                   nextst<=st3;
                   end if;
               when st4 => ale<='0';str<='0';oe<='0';lock<='0';
                   if eoc='1' then                   
                   nextst<=st5;
                   else 
                   nextst<=st4;
                   end if;
               when st5 => ale<='0';str<='0';oe<='1';lock<='0';
                   nextst<=st6;
               when st6 => ale<='0';str<='0';oe<='1';lock<='1';
                   nextst<=st7;
               when st7 => ale<='0';str<='0';oe<='1';lock<='1';
                   nextst<=st0;
               when others=>nextst<=st0;
            end case;
         end process com;
         data:process(lock)
             begin
                 if rising_edge(lock) then
                     regl<=din;
                 end if;
         end process data;
    dout<=regl;
end behav;