📄 clock.rpt
字号:
- 1 - C 16 OR2 ! 0 4 0 9 |time:U3|dy:U4|:263
- 3 - C 16 OR2 0 3 0 2 |time:U3|dy:U4|:302
- 4 - C 16 AND2 0 4 0 3 |time:U3|dy:U4|:307
- 1 - C 22 AND2 s ! 0 4 0 3 |time:U3|dy:U4|~346~1
- 1 - C 28 AND2 0 4 0 5 |time:U3|dy:U4|:346
- 2 - C 26 AND2 0 4 0 7 |time:U3|dy:U4|:351
- 2 - C 34 AND2 0 4 0 2 |time:U3|dy:U4|:553
- 1 - B 26 AND2 s ! 0 3 0 1 |time:U3|dy:U4|~781~1
- 2 - B 26 AND2 0 3 0 2 |time:U3|dy:U4|:781
- 1 - C 21 AND2 s 0 2 0 3 |time:U3|dy:U4|~995~1
- 1 - C 30 AND2 s 0 2 0 1 |time:U3|dy:U4|~1002~1
- 5 - C 24 AND2 s 0 3 0 3 |time:U3|dy:U4|~1002~2
- 7 - C 24 OR2 0 4 0 1 |time:U3|dy:U4|:1027
- 2 - C 16 OR2 s ! 0 4 0 1 |time:U3|dy:U4|~1034~1
- 6 - C 22 AND2 s ! 0 3 0 1 |time:U3|dy:U4|~1049~1
- 7 - C 22 OR2 s 0 3 0 3 |time:U3|dy:U4|~1073~1
- 1 - C 34 OR2 s 0 4 0 3 |time:U3|dy:U4|~1082~1
- 3 - C 30 OR2 0 4 0 1 |time:U3|dy:U4|:1087
- 3 - C 34 OR2 0 4 0 1 |time:U3|dy:U4|:1094
- 5 - C 10 AND2 0 2 0 1 |time:U3|mn:u5|LPM_ADD_SUB:190|addcore:adder|:55
- 6 - C 10 AND2 0 3 0 1 |time:U3|mn:u5|LPM_ADD_SUB:190|addcore:adder|:59
- 5 - C 16 AND2 0 2 0 1 |time:U3|mn:u5|LPM_ADD_SUB:199|addcore:adder|:55
- 3 - C 04 AND2 0 2 0 1 |time:U3|mn:u5|LPM_ADD_SUB:236|addcore:adder|:55
- 2 - C 04 DFFE 1 4 0 3 |time:U3|mn:u5|s13 (|time:U3|mn:u5|:15)
- 5 - C 04 DFFE 1 4 0 4 |time:U3|mn:u5|s12 (|time:U3|mn:u5|:16)
- 1 - C 04 DFFE 1 3 0 5 |time:U3|mn:u5|s11 (|time:U3|mn:u5|:17)
- 1 - C 08 DFFE ! 1 1 0 6 |time:U3|mn:u5|s10 (|time:U3|mn:u5|:18)
- 2 - C 10 DFFE 1 4 0 2 |time:U3|mn:u5|s23 (|time:U3|mn:u5|:19)
- 3 - C 10 DFFE 1 4 0 3 |time:U3|mn:u5|s22 (|time:U3|mn:u5|:20)
- 4 - C 10 DFFE 1 4 0 4 |time:U3|mn:u5|s21 (|time:U3|mn:u5|:21)
- 5 - C 11 DFFE 1 3 0 5 |time:U3|mn:u5|s20 (|time:U3|mn:u5|:22)
- 6 - C 16 DFFE 1 4 0 4 |time:U3|mn:u5|s33 (|time:U3|mn:u5|:23)
- 7 - C 16 DFFE 1 4 0 5 |time:U3|mn:u5|s32 (|time:U3|mn:u5|:24)
- 8 - C 16 DFFE 1 3 0 4 |time:U3|mn:u5|s31 (|time:U3|mn:u5|:25)
- 1 - C 01 DFFE ! 1 2 0 7 |time:U3|mn:u5|s30 (|time:U3|mn:u5|:26)
- 7 - C 10 OR2 s 0 3 0 1 |time:U3|mn:u5|~132~1
- 8 - C 10 OR2 s 0 3 0 1 |time:U3|mn:u5|~132~2
- 1 - C 10 OR2 ! 0 4 0 9 |time:U3|mn:u5|:132
- 1 - C 15 AND2 0 4 0 5 |time:U3|mn:u5|:137
- 4 - C 04 AND2 s 0 2 0 3 |time:U3|mn:u5|~275~1
- 4 - B 25 DFFE + 1 2 0 1 |time:U3|clkc2 (|time:U3|:66)
- 5 - B 25 DFFE + 1 2 0 1 |time:U3|clkc4 (|time:U3|:77)
- 5 - B 19 DFFE + 1 2 0 1 |time:U3|clkc6 (|time:U3|:92)
- 1 - B 23 OR2 1 2 0 9 |time:U3|:216
- 2 - B 25 OR2 1 2 0 9 |time:U3|:217
- 1 - B 25 OR2 1 2 0 9 |time:U3|:218
- 2 - B 19 OR2 1 2 0 12 |time:U3|:219
- 3 - A 23 DFFE 1 2 0 9 |trs38:U1|c2 (|trs38:U1|:9)
- 2 - A 23 DFFE 1 1 0 10 |trs38:U1|c1 (|trs38:U1|:10)
- 5 - A 23 DFFE 1 0 0 11 |trs38:U1|c0 (|trs38:U1|:11)
- 1 - B 27 AND2 0 3 0 3 |trs38:U1|:236
- 4 - B 19 AND2 0 3 0 2 |trs38:U1|:246
- 2 - B 29 AND2 0 3 0 4 |trs38:U1|:256
- 3 - B 25 AND2 0 3 0 2 |trs38:U1|:266
- 7 - B 33 AND2 0 3 0 4 |trs38:U1|:276
- 3 - F 01 AND2 s 0 4 0 1 |trs38:U1|~286~1
- 8 - F 11 AND2 s 0 4 0 1 |trs38:U1|~286~2
- 5 - E 03 AND2 s 0 4 0 1 |trs38:U1|~286~3
- 3 - E 03 AND2 s 0 4 0 1 |trs38:U1|~286~4
- 3 - E 01 AND2 s 0 4 0 1 |trs38:U1|~286~5
- 4 - F 09 AND2 s 0 4 0 1 |trs38:U1|~286~6
- 3 - F 09 AND2 s 0 4 0 1 |trs38:U1|~286~7
- 7 - F 11 AND2 s 0 4 0 1 |trs38:U1|~286~8
- 1 - F 12 AND2 s 0 2 0 8 |trs38:U1|~286~9
- 1 - B 34 OR2 ! 0 3 0 28 |trs38:U1|:286
- 7 - B 19 AND2 s 0 2 0 2 |trs38:U1|~445~1
- 3 - B 19 OR2 0 4 0 3 |trs38:U1|:445
- 1 - B 20 DFFE 0 1 0 30 cnt0 (:42)
- 7 - D 05 SOFT s ! 0 1 0 2 ced~1 (~44~1)
- 2 - B 20 DFFE + 1 2 0 25 ced (:44)
- 1 - B 30 OR2 ! 0 4 0 28 :362
- 1 - B 36 AND2 ! 1 2 0 26 :367
- 1 - B 19 OR2 1 2 0 25 :372
- 1 - B 28 OR2 s 0 4 0 1 ~890~1
- 5 - E 32 OR2 s 0 4 0 1 ~890~2
- 6 - F 30 OR2 0 3 1 0 :890
- 2 - B 28 OR2 s 0 4 0 1 ~905~1
- 6 - E 32 OR2 s 0 4 0 1 ~905~2
- 5 - F 30 OR2 0 3 1 0 :905
- 3 - B 28 OR2 s 0 4 0 1 ~920~1
- 1 - E 32 OR2 s 0 4 0 1 ~920~2
- 3 - F 29 OR2 0 3 1 0 :920
- 3 - B 21 OR2 s 0 4 0 1 ~935~1
- 3 - E 36 OR2 s 0 4 0 1 ~935~2
- 1 - F 30 OR2 0 3 1 0 :935
- 3 - B 31 OR2 s 0 4 0 1 ~950~1
- 3 - E 21 OR2 s 0 4 0 1 ~950~2
- 3 - D 33 OR2 0 3 1 0 :950
- 3 - B 26 OR2 s 0 4 0 1 ~965~1
- 2 - E 21 OR2 s 0 4 0 1 ~965~2
- 1 - D 33 OR2 0 3 1 0 :965
- 1 - B 32 OR2 s 0 4 0 1 ~980~1
- 2 - E 27 OR2 s 0 4 0 1 ~980~2
- 2 - D 35 OR2 0 3 1 0 :980
- 2 - B 35 OR2 s 0 4 0 1 ~995~1
- 3 - E 20 OR2 s 0 4 0 1 ~995~2
- 1 - D 35 OR2 0 3 1 0 :995
- 3 - A 14 OR2 s 0 4 0 1 ~1010~1
- 2 - D 07 OR2 0 3 1 0 :1010
- 4 - A 14 OR2 s 0 4 0 1 ~1025~1
- 1 - D 09 OR2 0 3 1 0 :1025
- 1 - A 02 OR2 s 0 4 0 1 ~1040~1
- 1 - D 27 OR2 0 3 1 0 :1040
- 4 - A 08 OR2 s 0 4 0 1 ~1055~1
- 1 - D 31 OR2 0 3 1 0 :1055
- 1 - A 15 OR2 s 0 4 0 1 ~1070~1
- 1 - D 03 OR2 0 3 1 0 :1070
- 7 - A 15 OR2 s 0 4 0 1 ~1085~1
- 1 - D 05 OR2 0 3 1 0 :1085
- 1 - A 01 OR2 s 0 4 0 1 ~1100~1
- 2 - D 05 OR2 0 3 1 0 :1100
- 1 - E 12 OR2 s 0 3 0 16 ~1115~1
- 7 - A 17 OR2 s 0 4 0 1 ~1115~2
- 1 - D 07 OR2 0 3 1 0 :1115
- 6 - F 11 OR2 s 0 4 0 1 ~1130~1
- 4 - F 11 OR2 0 4 1 0 :1130
- 2 - F 09 OR2 s 0 4 0 1 ~1145~1
- 6 - F 09 OR2 0 4 1 0 :1145
- 1 - F 09 OR2 s 0 4 0 1 ~1160~1
- 8 - F 09 OR2 0 4 1 0 :1160
- 2 - E 01 OR2 s 0 4 0 1 ~1175~1
- 1 - E 01 OR2 0 4 1 0 :1175
- 2 - E 03 OR2 s 0 4 0 1 ~1190~1
- 4 - E 03 OR2 0 4 1 0 :1190
- 1 - E 03 OR2 s 0 4 0 1 ~1205~1
- 8 - E 03 OR2 0 4 1 0 :1205
- 5 - F 11 OR2 s 0 4 0 1 ~1220~1
- 1 - F 11 OR2 0 4 1 0 :1220
- 3 - F 11 OR2 s 0 4 0 1 ~1235~1
- 2 - F 11 OR2 0 4 1 0 :1235
- 1 - D 34 OR2 1 3 1 0 :1252
- 6 - D 27 OR2 0 4 1 0 :1267
- 1 - E 29 OR2 1 3 1 0 :1282
- 3 - B 20 AND2 1 1 0 1 :1338
- 3 - B 36 AND2 1 1 0 8 :1346
- 2 - B 36 AND2 1 1 0 8 :1347
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\0zht\c2\clock.rpt
clock
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/144( 2%) 17/ 72( 23%) 0/ 72( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
B: 3/144( 2%) 0/ 72( 0%) 30/ 72( 41%) 2/16( 12%) 0/16( 0%) 0/16( 0%)
C: 6/144( 4%) 8/ 72( 11%) 13/ 72( 18%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
D: 8/144( 5%) 13/ 72( 18%) 17/ 72( 23%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
E: 6/144( 4%) 14/ 72( 19%) 19/ 72( 26%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
F: 6/144( 4%) 25/ 72( 34%) 11/ 72( 15%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/⌨️ 快捷键说明
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