📄 clock.rpt
字号:
|time:U3|dy:U4|lpm_add_sub:575|
|time:U3|dy:U4|lpm_add_sub:575|addcore:adder|
|time:U3|dy:U4|lpm_add_sub:575|altshift:result_ext_latency_ffs|
|time:U3|dy:U4|lpm_add_sub:575|altshift:carry_ext_latency_ffs|
|time:U3|dy:U4|lpm_add_sub:575|altshift:oflow_ext_latency_ffs|
|time:U3|dy:U4|lpm_add_sub:610|
|time:U3|dy:U4|lpm_add_sub:610|addcore:adder|
|time:U3|dy:U4|lpm_add_sub:610|altshift:result_ext_latency_ffs|
|time:U3|dy:U4|lpm_add_sub:610|altshift:carry_ext_latency_ffs|
|time:U3|dy:U4|lpm_add_sub:610|altshift:oflow_ext_latency_ffs|
|time:U3|dy:U4|lpm_add_sub:637|
|time:U3|dy:U4|lpm_add_sub:637|addcore:adder|
|time:U3|dy:U4|lpm_add_sub:637|altshift:result_ext_latency_ffs|
|time:U3|dy:U4|lpm_add_sub:637|altshift:carry_ext_latency_ffs|
|time:U3|dy:U4|lpm_add_sub:637|altshift:oflow_ext_latency_ffs|
|time:U3|dy:U4|lpm_add_sub:825|
|time:U3|dy:U4|lpm_add_sub:825|addcore:adder|
|time:U3|dy:U4|lpm_add_sub:825|altshift:result_ext_latency_ffs|
|time:U3|dy:U4|lpm_add_sub:825|altshift:carry_ext_latency_ffs|
|time:U3|dy:U4|lpm_add_sub:825|altshift:oflow_ext_latency_ffs|
|time:U3|dy:U4|lpm_add_sub:852|
|time:U3|dy:U4|lpm_add_sub:852|addcore:adder|
|time:U3|dy:U4|lpm_add_sub:852|altshift:result_ext_latency_ffs|
|time:U3|dy:U4|lpm_add_sub:852|altshift:carry_ext_latency_ffs|
|time:U3|dy:U4|lpm_add_sub:852|altshift:oflow_ext_latency_ffs|
|time:U3|mn:u5|
|time:U3|mn:u5|lpm_add_sub:190|
|time:U3|mn:u5|lpm_add_sub:190|addcore:adder|
|time:U3|mn:u5|lpm_add_sub:190|altshift:result_ext_latency_ffs|
|time:U3|mn:u5|lpm_add_sub:190|altshift:carry_ext_latency_ffs|
|time:U3|mn:u5|lpm_add_sub:190|altshift:oflow_ext_latency_ffs|
|time:U3|mn:u5|lpm_add_sub:199|
|time:U3|mn:u5|lpm_add_sub:199|addcore:adder|
|time:U3|mn:u5|lpm_add_sub:199|altshift:result_ext_latency_ffs|
|time:U3|mn:u5|lpm_add_sub:199|altshift:carry_ext_latency_ffs|
|time:U3|mn:u5|lpm_add_sub:199|altshift:oflow_ext_latency_ffs|
|time:U3|mn:u5|lpm_add_sub:236|
|time:U3|mn:u5|lpm_add_sub:236|addcore:adder|
|time:U3|mn:u5|lpm_add_sub:236|altshift:result_ext_latency_ffs|
|time:U3|mn:u5|lpm_add_sub:236|altshift:carry_ext_latency_ffs|
|time:U3|mn:u5|lpm_add_sub:236|altshift:oflow_ext_latency_ffs|
|time:U3|mn:u5|lpm_add_sub:245|
|time:U3|mn:u5|lpm_add_sub:245|addcore:adder|
|time:U3|mn:u5|lpm_add_sub:245|altshift:result_ext_latency_ffs|
|time:U3|mn:u5|lpm_add_sub:245|altshift:carry_ext_latency_ffs|
|time:U3|mn:u5|lpm_add_sub:245|altshift:oflow_ext_latency_ffs|
|nosy:U4|
|nosy:U4|cnt60oo:U1|
|nosy:U4|cnt60oo:U1|lpm_add_sub:114|
|nosy:U4|cnt60oo:U1|lpm_add_sub:114|addcore:adder|
|nosy:U4|cnt60oo:U1|lpm_add_sub:114|altshift:result_ext_latency_ffs|
|nosy:U4|cnt60oo:U1|lpm_add_sub:114|altshift:carry_ext_latency_ffs|
|nosy:U4|cnt60oo:U1|lpm_add_sub:114|altshift:oflow_ext_latency_ffs|
|nosy:U4|cnt60oo:U1|lpm_add_sub:139|
|nosy:U4|cnt60oo:U1|lpm_add_sub:139|addcore:adder|
|nosy:U4|cnt60oo:U1|lpm_add_sub:139|altshift:result_ext_latency_ffs|
|nosy:U4|cnt60oo:U1|lpm_add_sub:139|altshift:carry_ext_latency_ffs|
|nosy:U4|cnt60oo:U1|lpm_add_sub:139|altshift:oflow_ext_latency_ffs|
|nosy:U4|cnt24o:U2|
|nosy:U4|cnt24o:U2|lpm_add_sub:114|
|nosy:U4|cnt24o:U2|lpm_add_sub:114|addcore:adder|
|nosy:U4|cnt24o:U2|lpm_add_sub:114|altshift:result_ext_latency_ffs|
|nosy:U4|cnt24o:U2|lpm_add_sub:114|altshift:carry_ext_latency_ffs|
|nosy:U4|cnt24o:U2|lpm_add_sub:114|altshift:oflow_ext_latency_ffs|
|nosy:U4|cnt24o:U2|lpm_add_sub:139|
|nosy:U4|cnt24o:U2|lpm_add_sub:139|addcore:adder|
|nosy:U4|cnt24o:U2|lpm_add_sub:139|altshift:result_ext_latency_ffs|
|nosy:U4|cnt24o:U2|lpm_add_sub:139|altshift:carry_ext_latency_ffs|
|nosy:U4|cnt24o:U2|lpm_add_sub:139|altshift:oflow_ext_latency_ffs|
Device-Specific Information: d:\0zht\c2\clock.rpt
clock
***** Logic for device 'clock' compiled without errors.
Device: EP1K30TC144-1
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
Enable Lock Output = OFF
R R R R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E E E E E E E
S S S S S S S S S S S S S S V S S S S S S S S S S S S S
E E E E E E E E E V E E E E E C E E E E E E E V E E E E E E
R R R R R R R R R C R R R R R C R R R R R R R C R R R R R R
V V V V V G V V V V C V V V V G V I c G G G V V V V V V V C V V V V V V
E E E E E N E E E E I E E E E N E N l N N N E E E E E E E I E E E E E E
D D D D D D D D D D O D D D D D D T k D D D D D D D D D D O D D D D D D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GND
GND | 6 103 | VCCINT
RESERVED | 7 102 | RESERVED
set | 8 101 | RESERVED
date | 9 100 | RESERVED
clo | 10 99 | RESERVED
RESERVED | 11 98 | RESERVED
rst | 12 97 | RESERVED
RESERVED | 13 96 | RESERVED
RESERVED | 14 95 | RESERVED
GND | 15 94 | VCCIO
VCCINT | 16 93 | GND
RESERVED | 17 92 | RESERVED
RESERVED | 18 91 | RESERVED
RESERVED | 19 EP1K30TC144-1 90 | RESERVED
c1 | 20 89 | RESERVED
RESERVED | 21 88 | RESERVED
c2 | 22 87 | RESERVED
RESERVED | 23 86 | co63
VCCIO | 24 85 | VCCINT
GND | 25 84 | GND
c3 | 26 83 | co62
RESERVED | 27 82 | co61
RESERVED | 28 81 | co60
RESERVED | 29 80 | co53
co10 | 30 79 | co52
co11 | 31 78 | co51
co12 | 32 77 | ^MSEL0
co13 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
co20 | 36 73 | co50
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
c c c G c c R R V R R R R V R G V G G G G G R R V R R R c G c c c c V c
o o o N o o E E C E E E E C E N C N N N N N E E C E E E o N o o o o C o
2 2 2 D 3 3 S S C S S S S C S D C D D D D D S S C S S S 3 D 3 4 4 4 C 4
1 2 3 0 1 E E I E E E E I E _ _ E E I E E E 2 3 0 1 2 I 3
R R O R R R R N R C C R R O R R R O
V V V V V V T V K K V V V V V
E E E E E E E L L E E E E E
D D D D D D D K K D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: d:\0zht\c2\clock.rpt
clock
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
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