clock.rpt

功能更加完善的基于vhdl的数字时钟设计 有秒表

Project Information                                       d:\0zht\c2\clock.rpt

MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 12/14/2007 14:10:29

Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
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their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful


CLOCK


** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

clock     EP1K30TC144-1    5      27     0    0         0  %    280      16 %

User Pins:                 5      27     0  



Project Information                                       d:\0zht\c2\clock.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

clock@126                         clk
clock@10                          clo
clock@30                          co10
clock@31                          co11
clock@32                          co12
clock@33                          co13
clock@36                          co20
clock@37                          co21
clock@38                          co22
clock@39                          co23
clock@41                          co30
clock@42                          co31
clock@65                          co32
clock@67                          co33
clock@68                          co40
clock@69                          co41
clock@70                          co42
clock@72                          co43
clock@73                          co50
clock@78                          co51
clock@79                          co52
clock@80                          co53
clock@81                          co60
clock@82                          co61
clock@83                          co62
clock@86                          co63
clock@20                          c1
clock@22                          c2
clock@26                          c3
clock@9                           date
clock@12                          rst
clock@8                           set


Project Information                                       d:\0zht\c2\clock.rpt

** FILE HIERARCHY **



|lpm_add_sub:138|
|lpm_add_sub:138|addcore:adder|
|lpm_add_sub:138|altshift:result_ext_latency_ffs|
|lpm_add_sub:138|altshift:carry_ext_latency_ffs|
|lpm_add_sub:138|altshift:oflow_ext_latency_ffs|
|trs38:U1|
|trs38:U1|lpm_add_sub:21|
|trs38:U1|lpm_add_sub:21|addcore:adder|
|trs38:U1|lpm_add_sub:21|altshift:result_ext_latency_ffs|
|trs38:U1|lpm_add_sub:21|altshift:carry_ext_latency_ffs|
|trs38:U1|lpm_add_sub:21|altshift:oflow_ext_latency_ffs|
|second:U2|
|second:U2|cnt100:u1|
|second:U2|cnt100:u1|lpm_add_sub:153|
|second:U2|cnt100:u1|lpm_add_sub:153|addcore:adder|
|second:U2|cnt100:u1|lpm_add_sub:153|altshift:result_ext_latency_ffs|
|second:U2|cnt100:u1|lpm_add_sub:153|altshift:carry_ext_latency_ffs|
|second:U2|cnt100:u1|lpm_add_sub:153|altshift:oflow_ext_latency_ffs|
|second:U2|cnt100:u1|lpm_add_sub:180|
|second:U2|cnt100:u1|lpm_add_sub:180|addcore:adder|
|second:U2|cnt100:u1|lpm_add_sub:180|altshift:result_ext_latency_ffs|
|second:U2|cnt100:u1|lpm_add_sub:180|altshift:carry_ext_latency_ffs|
|second:U2|cnt100:u1|lpm_add_sub:180|altshift:oflow_ext_latency_ffs|
|second:U2|cnt60:u2|
|second:U2|cnt60:u2|lpm_add_sub:153|
|second:U2|cnt60:u2|lpm_add_sub:153|addcore:adder|
|second:U2|cnt60:u2|lpm_add_sub:153|altshift:result_ext_latency_ffs|
|second:U2|cnt60:u2|lpm_add_sub:153|altshift:carry_ext_latency_ffs|
|second:U2|cnt60:u2|lpm_add_sub:153|altshift:oflow_ext_latency_ffs|
|second:U2|cnt60:u2|lpm_add_sub:180|
|second:U2|cnt60:u2|lpm_add_sub:180|addcore:adder|
|second:U2|cnt60:u2|lpm_add_sub:180|altshift:result_ext_latency_ffs|
|second:U2|cnt60:u2|lpm_add_sub:180|altshift:carry_ext_latency_ffs|
|second:U2|cnt60:u2|lpm_add_sub:180|altshift:oflow_ext_latency_ffs|
|second:U2|cnt60o:u3|
|second:U2|cnt60o:u3|lpm_add_sub:146|
|second:U2|cnt60o:u3|lpm_add_sub:146|addcore:adder|
|second:U2|cnt60o:u3|lpm_add_sub:146|altshift:result_ext_latency_ffs|
|second:U2|cnt60o:u3|lpm_add_sub:146|altshift:carry_ext_latency_ffs|
|second:U2|cnt60o:u3|lpm_add_sub:146|altshift:oflow_ext_latency_ffs|
|second:U2|cnt60o:u3|lpm_add_sub:171|
|second:U2|cnt60o:u3|lpm_add_sub:171|addcore:adder|
|second:U2|cnt60o:u3|lpm_add_sub:171|altshift:result_ext_latency_ffs|
|second:U2|cnt60o:u3|lpm_add_sub:171|altshift:carry_ext_latency_ffs|
|second:U2|cnt60o:u3|lpm_add_sub:171|altshift:oflow_ext_latency_ffs|
|time:U3|
|time:U3|cnt60co:u1|
|time:U3|cnt60co:u1|lpm_add_sub:121|
|time:U3|cnt60co:u1|lpm_add_sub:121|addcore:adder|
|time:U3|cnt60co:u1|lpm_add_sub:121|altshift:result_ext_latency_ffs|
|time:U3|cnt60co:u1|lpm_add_sub:121|altshift:carry_ext_latency_ffs|
|time:U3|cnt60co:u1|lpm_add_sub:121|altshift:oflow_ext_latency_ffs|
|time:U3|cnt60co:u1|lpm_add_sub:148|
|time:U3|cnt60co:u1|lpm_add_sub:148|addcore:adder|
|time:U3|cnt60co:u1|lpm_add_sub:148|altshift:result_ext_latency_ffs|
|time:U3|cnt60co:u1|lpm_add_sub:148|altshift:carry_ext_latency_ffs|
|time:U3|cnt60co:u1|lpm_add_sub:148|altshift:oflow_ext_latency_ffs|
|time:U3|cnt60co:u2|
|time:U3|cnt60co:u2|lpm_add_sub:121|
|time:U3|cnt60co:u2|lpm_add_sub:121|addcore:adder|
|time:U3|cnt60co:u2|lpm_add_sub:121|altshift:result_ext_latency_ffs|
|time:U3|cnt60co:u2|lpm_add_sub:121|altshift:carry_ext_latency_ffs|
|time:U3|cnt60co:u2|lpm_add_sub:121|altshift:oflow_ext_latency_ffs|
|time:U3|cnt60co:u2|lpm_add_sub:148|
|time:U3|cnt60co:u2|lpm_add_sub:148|addcore:adder|
|time:U3|cnt60co:u2|lpm_add_sub:148|altshift:result_ext_latency_ffs|
|time:U3|cnt60co:u2|lpm_add_sub:148|altshift:carry_ext_latency_ffs|
|time:U3|cnt60co:u2|lpm_add_sub:148|altshift:oflow_ext_latency_ffs|
|time:U3|cnt24:u3|
|time:U3|cnt24:u3|lpm_add_sub:121|
|time:U3|cnt24:u3|lpm_add_sub:121|addcore:adder|
|time:U3|cnt24:u3|lpm_add_sub:121|altshift:result_ext_latency_ffs|
|time:U3|cnt24:u3|lpm_add_sub:121|altshift:carry_ext_latency_ffs|
|time:U3|cnt24:u3|lpm_add_sub:121|altshift:oflow_ext_latency_ffs|
|time:U3|cnt24:u3|lpm_add_sub:148|
|time:U3|cnt24:u3|lpm_add_sub:148|addcore:adder|
|time:U3|cnt24:u3|lpm_add_sub:148|altshift:result_ext_latency_ffs|
|time:U3|cnt24:u3|lpm_add_sub:148|altshift:carry_ext_latency_ffs|
|time:U3|cnt24:u3|lpm_add_sub:148|altshift:oflow_ext_latency_ffs|
|time:U3|dy:U4|
|time:U3|dy:U4|lpm_add_sub:382|
|time:U3|dy:U4|lpm_add_sub:382|addcore:adder|
|time:U3|dy:U4|lpm_add_sub:382|altshift:result_ext_latency_ffs|
|time:U3|dy:U4|lpm_add_sub:382|altshift:carry_ext_latency_ffs|
|time:U3|dy:U4|lpm_add_sub:382|altshift:oflow_ext_latency_ffs|
|time:U3|dy:U4|lpm_add_sub:409|
|time:U3|dy:U4|lpm_add_sub:409|addcore:adder|
|time:U3|dy:U4|lpm_add_sub:409|altshift:result_ext_latency_ffs|
|time:U3|dy:U4|lpm_add_sub:409|altshift:carry_ext_latency_ffs|
|time:U3|dy:U4|lpm_add_sub:409|altshift:oflow_ext_latency_ffs|