📄 clock.map.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version" { } { } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 08 19:11:52 2007 " "Info: Processing started: Sat Dec 08 19:11:52 2007" { } { } 0 0 "Processing started: %1!s!" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock -c clock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock" { } { } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "clock.vhd 28 14 " "Warning: Using design file clock.vhd, which is not specified as a design file for the current project, but contains definitions for 28 design units and 14 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock-behav " "Info: Found design unit 1: clock-behav" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 9 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 trs38-behav " "Info: Found design unit 2: trs38-behav" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 126 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 second-show " "Info: Found design unit 3: second-show" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 221 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 cnt100-wav " "Info: Found design unit 4: cnt100-wav" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 261 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 cnt60-wav " "Info: Found design unit 5: cnt60-wav" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 299 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "6 cnt60o-wav " "Info: Found design unit 6: cnt60o-wav" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 336 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "7 time-show " "Info: Found design unit 7: time-show" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 371 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "8 cnt60co-wav " "Info: Found design unit 8: cnt60co-wav" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 465 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "9 cnt24-wav " "Info: Found design unit 9: cnt24-wav" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 498 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "10 dy-grw " "Info: Found design unit 10: dy-grw" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 533 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "11 mn-grw " "Info: Found design unit 11: mn-grw" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 600 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "12 nosy-behav " "Info: Found design unit 12: nosy-behav" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 636 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "13 cnt60oo-wav " "Info: Found design unit 13: cnt60oo-wav" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 662 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "14 cnt24o-wav " "Info: Found design unit 14: cnt24o-wav" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 689 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 4 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 trs38 " "Info: Found entity 2: trs38" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 122 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 second " "Info: Found entity 3: second" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 217 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 cnt100 " "Info: Found entity 4: cnt100" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 256 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 cnt60 " "Info: Found entity 5: cnt60" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 294 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "6 cnt60o " "Info: Found entity 6: cnt60o" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 332 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "7 time " "Info: Found entity 7: time" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 366 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "8 cnt60co " "Info: Found entity 8: cnt60co" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 460 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "9 cnt24 " "Info: Found entity 9: cnt24" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 493 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "10 dy " "Info: Found entity 10: dy" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 527 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "11 mn " "Info: Found entity 11: mn" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 596 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "12 nosy " "Info: Found entity 12: nosy" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 632 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "13 cnt60oo " "Info: Found entity 13: cnt60oo" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 658 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "14 cnt24o " "Info: Found entity 14: cnt24o" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 685 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock " "Info: Elaborating entity \"clock\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 clock.vhd(63) " "Warning (10492): VHDL Process Statement warning at clock.vhd(63): signal \"s1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 63 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s2 clock.vhd(64) " "Warning (10492): VHDL Process Statement warning at clock.vhd(64): signal \"s2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 64 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s3 clock.vhd(65) " "Warning (10492): VHDL Process Statement warning at clock.vhd(65): signal \"s3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 65 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s4 clock.vhd(66) " "Warning (10492): VHDL Process Statement warning at clock.vhd(66): signal \"s4\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 66 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s5 clock.vhd(67) " "Warning (10492): VHDL Process Statement warning at clock.vhd(67): signal \"s5\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 67 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s6 clock.vhd(68) " "Warning (10492): VHDL Process Statement warning at clock.vhd(68): signal \"s6\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 68 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min clock.vhd(72) " "Warning (10492): VHDL Process Statement warning at clock.vhd(72): signal \"min\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 72 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour clock.vhd(72) " "Warning (10492): VHDL Process Statement warning at clock.vhd(72): signal \"hour\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 72 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s7 clock.vhd(73) " "Warning (10492): VHDL Process Statement warning at clock.vhd(73): signal \"s7\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 73 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s8 clock.vhd(74) " "Warning (10492): VHDL Process Statement warning at clock.vhd(74): signal \"s8\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 74 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s9 clock.vhd(75) " "Warning (10492): VHDL Process Statement warning at clock.vhd(75): signal \"s9\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 75 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s10 clock.vhd(76) " "Warning (10492): VHDL Process Statement warning at clock.vhd(76): signal \"s10\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 76 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s11 clock.vhd(77) " "Warning (10492): VHDL Process Statement warning at clock.vhd(77): signal \"s11\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 77 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s12 clock.vhd(78) " "Warning (10492): VHDL Process Statement warning at clock.vhd(78): signal \"s12\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 78 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min clock.vhd(80) " "Warning (10492): VHDL Process Statement warning at clock.vhd(80): signal \"min\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 80 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour clock.vhd(81) " "Warning (10492): VHDL Process Statement warning at clock.vhd(81): signal \"hour\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 81 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clo clock.vhd(82) " "Warning (10492): VHDL Process Statement warning at clock.vhd(82): signal \"clo\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 82 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
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