clock.hif

功能更加完善的基于vhdl的数字时钟设计 有秒表

Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
2
11
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
altsyn.lmf
-- Start Partition --
-- End Partition --
# entity
clock
# storage
db|clock.(0).cnf
db|clock.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock.vhd
a779ff3f3e3998d34f858b0be201fb4
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
|
}
# end
# entity
trs38
# storage
db|clock.(1).cnf
db|clock.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock.vhd
a779ff3f3e3998d34f858b0be201fb4
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
trs38:U1
}
# end
# entity
second
# storage
db|clock.(2).cnf
db|clock.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock.vhd
a779ff3f3e3998d34f858b0be201fb4
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(co1)
3 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
second:U2
}
# end
# entity
cnt100
# storage
db|clock.(3).cnf
db|clock.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock.vhd
a779ff3f3e3998d34f858b0be201fb4
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(co1)
3 downto 0
PARAMETER_STRING
USR
 constraint(co2)
3 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
second:U2|cnt100:u1
}
# end
# entity
cnt60
# storage
db|clock.(4).cnf
db|clock.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock.vhd
a779ff3f3e3998d34f858b0be201fb4
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(co1)
3 downto 0
PARAMETER_STRING
USR
 constraint(co2)
3 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
second:U2|cnt60:u2
}
# end
# entity
cnt60o
# storage
db|clock.(5).cnf
db|clock.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock.vhd
a779ff3f3e3998d34f858b0be201fb4
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(co1)
3 downto 0
PARAMETER_STRING
USR
 constraint(co2)
3 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
second:U2|cnt60o:u3
}
# end
# entity
time
# storage
db|clock.(6).cnf
db|clock.(6).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock.vhd
a779ff3f3e3998d34f858b0be201fb4
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(co1)
3 downto 0
PARAMETER_STRING
USR
 constraint(co2)
3 downto 0
PARAMETER_STRING
USR
 constraint(co3)
3 downto 0
PARAMETER_STRING
USR
 constraint(co4)
3 downto 0
PARAMETER_STRING
USR
 constraint(co5)
3 downto 0
PARAMETER_STRING
USR
 constraint(co6)
3 downto 0
PARAMETER_STRING
USR
 constraint(co7)
3 downto 0
PARAMETER_STRING
USR
 constraint(co8)
3 downto 0
PARAMETER_STRING
USR
 constraint(co9)
3 downto 0
PARAMETER_STRING
USR
 constraint(co01)
3 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
time:U3
}
# end
# entity
cnt60co
# storage
db|clock.(7).cnf
db|clock.(7).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock.vhd
a779ff3f3e3998d34f858b0be201fb4
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(co1)
3 downto 0
PARAMETER_STRING
USR
 constraint(co2)
3 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
time:U3|cnt60co:u1
time:U3|cnt60co:u2
}
# end
# entity
cnt24
# storage
db|clock.(8).cnf
db|clock.(8).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock.vhd
a779ff3f3e3998d34f858b0be201fb4
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(co1)
3 downto 0
PARAMETER_STRING
USR
 constraint(co2)
3 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
time:U3|cnt24:u3
}
# end
# entity
dy
# storage
db|clock.(9).cnf
db|clock.(9).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock.vhd
a779ff3f3e3998d34f858b0be201fb4
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(mon)
3 downto 0
PARAMETER_STRING
USR
 constraint(co1)
3 downto 0
PARAMETER_STRING
USR
 constraint(co2)
3 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
time:U3|dy:U4
}
# end
# entity
mn
# storage
db|clock.(10).cnf
db|clock.(10).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock.vhd
a779ff3f3e3998d34f858b0be201fb4
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(co1)
3 downto 0
PARAMETER_STRING
USR
 constraint(co2)
3 downto 0
PARAMETER_STRING
USR
 constraint(co3)
3 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
time:U3|mn:u5
}
# end
# entity
nosy
# storage
db|clock.(11).cnf
db|clock.(11).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock.vhd
a779ff3f3e3998d34f858b0be201fb4
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(co1)
3 downto 0
PARAMETER_STRING
USR
 constraint(co2)
3 downto 0
PARAMETER_STRING
USR
 constraint(co3)
3 downto 0
PARAMETER_STRING
USR
 constraint(co4)
3 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
nosy:U4
}
# end
# entity
cnt60oo
# storage
db|clock.(12).cnf
db|clock.(12).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock.vhd
a779ff3f3e3998d34f858b0be201fb4
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(co1)
3 downto 0
PARAMETER_STRING
USR
 constraint(co2)
3 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
nosy:U4|cnt60oo:U1
}
# end
# entity
cnt24o
# storage
db|clock.(13).cnf
db|clock.(13).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock.vhd
a779ff3f3e3998d34f858b0be201fb4
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(co1)
3 downto 0
PARAMETER_STRING
USR
 constraint(co2)
3 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
nosy:U4|cnt24o:U2
}
# end
# entity
lpm_counter
# storage
db|clock.(14).cnf
db|clock.(14).cnf
# case_insensitive
# source_file
c:|altera|quartus51|libraries|megafunctions|lpm_counter.tdf
a52725e432c6afb55468eb62553a3d9e
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
4
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
UP
PARAMETER_UNKNOWN
USR
LPM_MODULUS
0
PARAMETER_UNKNOWN
DEF
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
ACEX1K
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
ON
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
}
# used_port {
sclr
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# include_file {
c:|altera|quartus51|libraries|megafunctions|lpm_constant.inc
dcde44eee59335c1e2fe75d574f9646
c:|altera|quartus51|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
c:|altera|quartus51|libraries|megafunctions|lpm_add_sub.inc
7d9a33dd39f13aa690c3d0edd88351
c:|altera|quartus51|libraries|megafunctions|cmpconst.inc
e61874547688138e6fc0b49ff8760
c:|altera|quartus51|libraries|megafunctions|lpm_compare.inc
aec4ea1b78f4cda1c3effe18f1abbf63
c:|altera|quartus51|libraries|megafunctions|lpm_counter.inc
758886b0947dd67e65ec58adda9b948
c:|altera|quartus51|libraries|megafunctions|dffeea.inc
55d29d20f7e852c37746bec4e2495ec
c:|altera|quartus51|libraries|megafunctions|alt_synch_counter.inc
e64d362a7450ad9895aa7e1e5dc2b42a
c:|altera|quartus51|libraries|megafunctions|alt_synch_counter_f.inc
88e2e3ac71decf106c8d913bf441832f
c:|altera|quartus51|libraries|megafunctions|alt_counter_f10ke.inc
d8a92a43831e9df2804dcf9a927e20
c:|altera|quartus51|libraries|megafunctions|alt_counter_stratix.inc
587bf41cd15486161ec3eb5a1fef4c2
c:|altera|quartus51|libraries|megafunctions|aglobal51.inc
c49d61e8168d42962ec885e3e17640c2
}
# end
# entity
alt_counter_f10ke
# storage
db|clock.(15).cnf
db|clock.(15).cnf
# case_insensitive
# source_file
c:|altera|quartus51|libraries|megafunctions|alt_counter_f10ke.tdf
185629c1c9217b8eedf38296709cc0
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
4
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
UP
PARAMETER_UNKNOWN
USR
LPM_MODULUS
0
PARAMETER_UNKNOWN
USR
LPM_SVALUE
15
PARAMETER_UNKNOWN
DEF
LPM_AVALUE
15
PARAMETER_UNKNOWN
DEF
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CASCADE_CHAIN_LENGTH
2
CASCADE_CHAIN_LENGTH
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH