clock.tan.qmsg

功能更加完善的基于vhdl的数字时钟设计 有秒表

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clo register register cnt\[0\] cnt\[0\] 200.0 MHz Internal " "Info: Clock \"clo\" Internal fmax is restricted to 200.0 MHz between source register \"cnt\[0\]\" and destination register \"cnt\[0\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.100 ns + Longest register register " "Info: + Longest register to register delay is 1.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[0\] 1 REG LC5_B10 27 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_B10; Fanout = 27; REG Node = 'cnt\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/0zht/C2/db/clock.quartus_db" { Floorplan "D:/0zht/C2/" "" "" { cnt[0] } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.800 ns) 1.100 ns cnt\[0\] 2 REG LC5_B10 27 " "Info: 2: + IC(0.300 ns) + CELL(0.800 ns) = 1.100 ns; Loc. = LC5_B10; Fanout = 27; REG Node = 'cnt\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/0zht/C2/db/clock.quartus_db" { Floorplan "D:/0zht/C2/" "" "1.100 ns" { cnt[0] cnt[0] } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.800 ns ( 72.73 % ) " "Info: Total cell delay = 0.800 ns ( 72.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 27.27 % ) " "Info: Total interconnect delay = 0.300 ns ( 27.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/0zht/C2/db/clock.quartus_db" { Floorplan "D:/0zht/C2/" "" "1.100 ns" { cnt[0] cnt[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.100 ns" { cnt[0] cnt[0] } { 0.000ns 0.300ns } { 0.000ns 0.800ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clo destination 3.700 ns + Shortest register " "Info: + Shortest clock path from clock \"clo\" to destination register is 3.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clo 1 CLK PIN_56 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_56; Fanout = 6; CLK Node = 'clo'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/0zht/C2/db/clock.quartus_db" { Floorplan "D:/0zht/C2/" "" "" { clo } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 3.400 ns cecl 2 COMB LC7_B10 1 " "Info: 2: + IC(0.000 ns) + CELL(1.400 ns) = 3.400 ns; Loc. = LC7_B10; Fanout = 1; COMB Node = 'cecl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/0zht/C2/db/clock.quartus_db" { Floorplan "D:/0zht/C2/" "" "1.400 ns" { clo cecl } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 3.700 ns cnt\[0\] 3 REG LC5_B10 27 " "Info: 3: + IC(0.300 ns) + CELL(0.000 ns) = 3.700 ns; Loc. = LC5_B10; Fanout = 27; REG Node = 'cnt\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/0zht/C2/db/clock.quartus_db" { Floorplan "D:/0zht/C2/" "" "0.300 ns" { cecl cnt[0] } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 91.89 % ) " "Info: Total cell delay = 3.400 ns ( 91.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 8.11 % ) " "Info: Total interconnect delay = 0.300 ns ( 8.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/0zht/C2/db/clock.quartus_db" { Floorplan "D:/0zht/C2/" "" "3.700 ns" { clo cecl cnt[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.700 ns" { clo clo~out cecl cnt[0] } { 0.000ns 0.000ns 0.000ns 0.300ns } { 0.000ns 2.000ns 1.400ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clo source 3.700 ns - Longest register " "Info: - Longest clock path from clock \"clo\" to source register is 3.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clo 1 CLK PIN_56 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_56; Fanout = 6; CLK Node = 'clo'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/0zht/C2/db/clock.quartus_db" { Floorplan "D:/0zht/C2/" "" "" { clo } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 3.400 ns cecl 2 COMB LC7_B10 1 " "Info: 2: + IC(0.000 ns) + CELL(1.400 ns) = 3.400 ns; Loc. = LC7_B10; Fanout = 1; COMB Node = 'cecl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/0zht/C2/db/clock.quartus_db" { Floorplan "D:/0zht/C2/" "" "1.400 ns" { clo cecl } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 3.700 ns cnt\[0\] 3 REG LC5_B10 27 " "Info: 3: + IC(0.300 ns) + CELL(0.000 ns) = 3.700 ns; Loc. = LC5_B10; Fanout = 27; REG Node = 'cnt\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/0zht/C2/db/clock.quartus_db" { Floorplan "D:/0zht/C2/" "" "0.300 ns" { cecl cnt[0] } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 91.89 % ) " "Info: Total cell delay = 3.400 ns ( 91.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 8.11 % ) " "Info: Total interconnect delay = 0.300 ns ( 8.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/0zht/C2/db/clock.quartus_db" { Floorplan "D:/0zht/C2/" "" "3.700 ns" { clo cecl cnt[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.700 ns" { clo clo~out cecl cnt[0] } { 0.000ns 0.000ns 0.000ns 0.300ns } { 0.000ns 2.000ns 1.400ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/0zht/C2/db/clock.quartus_db" { Floorplan "D:/0zht/C2/" "" "3.700 ns" { clo cecl cnt[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.700 ns" { clo clo~out cecl cnt[0] } { 0.000ns 0.000ns 0.000ns 0.300ns } { 0.000ns 2.000ns 1.400ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/0zht/C2/db/clock.quartus_db" { Floorplan "D:/0zht/C2/" "" "3.700 ns" { clo cecl cnt[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.700 ns" { clo clo~out cecl cnt[0] } { 0.000ns 0.000ns 0.000ns 0.300ns } { 0.000ns 2.000ns 1.400ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/0zht/C2/db/clock.quartus_db" { Floorplan "D:/0zht/C2/" "" "1.100 ns" { cnt[0] cnt[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.100 ns" { cnt[0] cnt[0] } { 0.000ns 0.300ns } { 0.000ns 0.800ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/0zht/C2/db/clock.quartus_db" { Floorplan "D:/0zht/C2/" "" "3.700 ns" { clo cecl cnt[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.700 ns" { clo clo~out cecl cnt[0] } { 0.000ns 0.000ns 0.000ns 0.300ns } { 0.000ns 2.000ns 1.400ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/0zht/C2/db/clock.quartus_db" { Floorplan "D:/0zht/C2/" "" "3.700 ns" { clo cecl cnt[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.700 ns" { clo clo~out cecl cnt[0] } { 0.000ns 0.000ns 0.000ns 0.300ns } { 0.000ns 2.000ns 1.400ns 0.000ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/0zht/C2/db/clock.quartus_db" { Floorplan "D:/0zht/C2/" "" "" { cnt[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { cnt[0] } {  } {  } } } { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 36 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "date register time:U3\|dy:U4\|s1\[2\] register time:U3\|dy:U4\|lpm_counter:s2_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 77.52 MHz 12.9 ns Internal " "Info: Clock \"date\" has Internal fmax of 77.52 MHz between source register \"time:U3\|dy:U4\|s1\[2\]\" and destination register \"time:U3\|dy:U4\|lpm_counter:s2_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]\" (period= 12.9 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.800 ns + Longest register register " "Info: + Longest register to register delay is 11.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns time:U3\|dy:U4\|s1\[2\] 1 REG LC6_B22 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_B22; Fanout = 6; REG Node = 'time:U3\|dy:U4\|s1\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/0zht/C2/db/clock.quartus_db" { Floorplan "D:/0zht/C2/" "" "" { time:U3|dy:U4|s1[2] } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 539 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 1.900 ns time:U3\|dy:U4\|Equal~239 2 COMB LC5_B22 1 " "Info: 2: + IC(0.300 ns) + CELL(1.600 ns) = 1.900 ns; Loc. = LC5_B22; Fanout = 1; COMB Node = 'time:U3\|dy:U4\|Equal~239'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/0zht/C2/db/clock.quartus_db" { Floorplan "D:/0zht/C2/" "" "1.900 ns" { time:U3|dy:U4|s1[2] time:U3|dy:U4|Equal~239 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.400 ns) 4.300 ns time:U3\|dy:U4\|process0~198 3 COMB LC3_B23 3 " "Info: 3: + IC(1.000 ns) + CELL(1.400 ns) = 4.300 ns; Loc. = LC3_B23; Fanout = 3; COMB Node = 'time:U3\|dy:U4\|process0~198'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/0zht/C2/db/clock.quartus_db" { Floorplan "D:/0zht/C2/" "" "2.400 ns" { time:U3|dy:U4|Equal~239 time:U3|dy:U4|process0~198 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 6.000 ns time:U3\|dy:U4\|process0~200 4 COMB LC8_B23 2 " "Info: 4: + IC(0.300 ns) + CELL(1.400 ns) = 6.000 ns; Loc. = LC8_B23; Fanout = 2; COMB Node = 'time:U3\|dy:U4\|process0~200'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/0zht/C2/db/clock.quartus_db" { Floorplan "D:/0zht/C2/" "" "1.700 ns" { time:U3|dy:U4|process0~198 time:U3|dy:U4|process0~200 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.700 ns) 8.000 ns time:U3\|dy:U4\|s2~144 5 COMB LC2_B23 1 " "Info: 5: + IC(0.300 ns) + CELL(1.700 ns) = 8.000 ns; Loc. = LC2_B23; Fanout = 1; COMB Node = 'time:U3\|dy:U4\|s2~144'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/0zht/C2/db/clock.quartus_db" { Floorplan "D:/0zht/C2/" "" "2.000 ns" { time:U3|dy:U4|process0~200 time:U3|dy:U4|s2~144 } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 534 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.600 ns) 10.500 ns time:U3\|dy:U4\|s2~146 6 COMB LC7_B24 7 " "Info: 6: + IC(0.900 ns) + CELL(1.600 ns) = 10.500 ns; Loc. = LC7_B24; Fanout = 7; COMB Node = 'time:U3\|dy:U4\|s2~146'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/0zht/C2/db/clock.quartus_db" { Floorplan "D:/0zht/C2/" "" "2.500 ns" { time:U3|dy:U4|s2~144 time:U3|dy:U4|s2~146 } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "D:/0zht/C2/clock.vhd" 534 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.000 ns) 11.800 ns time:U3\|dy:U4\|lpm_counter:s2_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 7 REG LC6_B24 3 " "Info: 7: + IC(0.300 ns) + CELL(1.000 ns) = 11.800 ns; Loc. = LC6_B24; Fanout = 3; REG Node = 'time:U3\|dy:U4\|lpm_counter:s2_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/0zht/C2/db/clock.quartus_db" { Floorplan "D:/0zht/C2/" "" "1.300 ns" { time:U3|dy:U4|s2~146 time:U3|dy:U4|lpm_counter:s2_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.700 ns ( 73.73 % ) " "Info: Total cell delay = 8.700 ns ( 73.73 % )" {  } {  } 0 0 "To