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📄 clock.vho

📁 功能更加完善的基于vhdl的数字时钟设计 有秒表
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	modesel : IN STD_LOGIC_VECTOR(10 DOWNTO 0));
END COMPONENT;


COMPONENT INV
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;

COMPONENT AND1
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;
BEGIN

ww_set <= set;
ww_date <= date;
ww_clo <= clo;
ww_clk <= clk;
ww_rst <= rst;
co1 <= ww_co1;
co2 <= ww_co2;
co3 <= ww_co3;
co4 <= ww_co4;
co5 <= ww_co5;
co6 <= ww_co6;
c1 <= ww_c1;
c2 <= ww_c2;
c3 <= ww_c3;

gnd <= '0';
vcc <= '1';
GNDs <= (OTHERS => '0');
VCCs <= (OTHERS => '1');

\U3|u5|add~143_I_modesel\ <= "1000001";
\U3|u5|add~143_I_pathsel\ <= "0000001100";
\U3|u5|s3[3]~I_modesel\ <= "1000001";
\U3|u5|s3[3]~I_pathsel\ <= "0000001111";
\U3|U4|process0~200_I_modesel\ <= "1000001";
\U3|U4|process0~200_I_pathsel\ <= "0000001110";
\U4|U1|process0~24_I_modesel\ <= "1000001";
\U4|U1|process0~24_I_pathsel\ <= "0000001110";
\U2|u1|c~0_I_modesel\ <= "1000001";
\U2|u1|c~0_I_pathsel\ <= "0000001100";
\U4|U2|Equal~49_I_modesel\ <= "1000001";
\U4|U2|Equal~49_I_pathsel\ <= "0000001111";
\U3|u3|Equal~49_I_modesel\ <= "1000001";
\U3|u3|Equal~49_I_pathsel\ <= "0000001111";
\U3|u5|Equal~51_I_modesel\ <= "1000001";
\U3|u5|Equal~51_I_pathsel\ <= "0000001111";
\U3|u5|add~144_I_modesel\ <= "1000001";
\U3|u5|add~144_I_pathsel\ <= "0000001100";
\U3|U4|c~338_I_modesel\ <= "1000001";
\U3|U4|c~338_I_pathsel\ <= "0000001000";
\set~I_modesel\ <= "01010000001";
\U1|c[0]~I_modesel\ <= "1000001";
\U1|c[0]~I_pathsel\ <= "0000001000";
\U1|c[1]~I_modesel\ <= "1000001";
\U1|c[1]~I_pathsel\ <= "0000001100";
\U1|c[2]~I_modesel\ <= "1000001";
\U1|c[2]~I_pathsel\ <= "0000001110";
\clo~I_modesel\ <= "01010000001";
\cecl~I_modesel\ <= "1000001";
\cecl~I_pathsel\ <= "0000001111";
\cnt[0]~I_modesel\ <= "1000001";
\cnt[0]~I_pathsel\ <= "0000001000";
\U1|sday~88_I_modesel\ <= "1000001";
\U1|sday~88_I_pathsel\ <= "0000001110";
\date~I_modesel\ <= "01010000001";
\clk~I_modesel\ <= "01010000001";
\ced~I_modesel\ <= "1000001";
\ced~I_pathsel\ <= "0000001110";
\U2|u1|s1[0]~I_modesel\ <= "0100001";
\U2|u1|s1[0]~I_pathsel\ <= "0000001000";
\co1~1387_I_modesel\ <= "1000001";
\co1~1387_I_pathsel\ <= "0000001111";
\process2~4_I_modesel\ <= "1000001";
\process2~4_I_pathsel\ <= "0000001110";
\co1~1386_I_modesel\ <= "1000001";
\co1~1386_I_pathsel\ <= "0000001110";
\U3|u1|s1[0]~I_modesel\ <= "1000001";
\U3|u1|s1[0]~I_pathsel\ <= "0000001000";
\co1~1401_I_modesel\ <= "1000001";
\co1~1401_I_pathsel\ <= "0000001111";
\co1~1385_I_modesel\ <= "1000001";
\co1~1385_I_pathsel\ <= "0000001111";
\scmin~9_I_modesel\ <= "1000001";
\scmin~9_I_pathsel\ <= "0000001111";
\U4|U1|s1[0]~I_modesel\ <= "1000001";
\U4|U1|s1[0]~I_pathsel\ <= "0000001000";
\co1~1400_I_modesel\ <= "1000001";
\co1~1400_I_pathsel\ <= "0000001111";
\co1~1412_I_modesel\ <= "1000001";
\co1~1412_I_pathsel\ <= "0000001111";
\U2|u1|s1[2]~I_modesel\ <= "0100001";
\U2|u1|s1[2]~I_pathsel\ <= "0000001110";
\U2|u1|s1~74_I_modesel\ <= "1000001";
\U2|u1|s1~74_I_pathsel\ <= "0000001111";
\U2|u1|s1[3]~I_modesel\ <= "0100001";
\U2|u1|s1[3]~I_pathsel\ <= "0000001000";
\U2|u1|Equal~40_I_modesel\ <= "1000001";
\U2|u1|Equal~40_I_pathsel\ <= "0000001111";
\U2|u1|s1[1]~I_modesel\ <= "0100001";
\U2|u1|s1[1]~I_pathsel\ <= "0000001110";
\U3|u1|s1[2]~I_modesel\ <= "1000001";
\U3|u1|s1[2]~I_pathsel\ <= "0000001110";
\U3|u1|s1[3]~I_modesel\ <= "1000001";
\U3|u1|s1[3]~I_pathsel\ <= "0000001111";
\U3|u1|s1[1]~I_modesel\ <= "1000001";
\U3|u1|s1[1]~I_pathsel\ <= "0000001111";
\rst~I_modesel\ <= "01010000001";
\smon~2_I_modesel\ <= "1000001";
\smon~2_I_pathsel\ <= "0000001100";
\U3|u5|s3[0]~I_modesel\ <= "1000001";
\U3|u5|s3[0]~I_pathsel\ <= "0000001100";
\U3|U4|Equal~238_I_modesel\ <= "1000001";
\U3|U4|Equal~238_I_pathsel\ <= "0000001111";
\U3|U4|process0~204_I_modesel\ <= "1000001";
\U3|U4|process0~204_I_pathsel\ <= "0000001111";
\U3|U4|Equal~237_I_modesel\ <= "1000001";
\U3|U4|Equal~237_I_pathsel\ <= "0000001111";
\U3|U4|s1~816_I_modesel\ <= "1000001";
\U3|U4|s1~816_I_pathsel\ <= "0000001111";
\U3|U4|s1~819_I_modesel\ <= "1000001";
\U3|U4|s1~819_I_pathsel\ <= "0000001111";
\process2~80_I_modesel\ <= "1000001";
\process2~80_I_pathsel\ <= "0000001100";
\U3|u1|Equal~40_I_modesel\ <= "1000001";
\U3|u1|Equal~40_I_pathsel\ <= "0000001111";
\U3|u1|add_rtl_4|adder|result_node|cs_buffer[0]~I_modesel\ <= "1000010";
\U3|u1|add_rtl_4|adder|result_node|cs_buffer[0]~I_pathsel\ <= "0011000011";
\U3|u1|s2[0]~I_modesel\ <= "1000001";
\U3|u1|s2[0]~I_pathsel\ <= "0000001000";
\U3|u1|add_rtl_4|adder|result_node|cs_buffer[1]~I_modesel\ <= "1000010";
\U3|u1|add_rtl_4|adder|result_node|cs_buffer[1]~I_pathsel\ <= "0110010010";
\U3|u1|s2[1]~I_modesel\ <= "1000001";
\U3|u1|s2[1]~I_pathsel\ <= "0000001111";
\U3|u1|add_rtl_4|adder|result_node|cs_buffer[2]~I_modesel\ <= "1000010";
\U3|u1|add_rtl_4|adder|result_node|cs_buffer[2]~I_pathsel\ <= "0110010010";
\U3|u1|s2[2]~I_modesel\ <= "1000001";
\U3|u1|s2[2]~I_pathsel\ <= "0000001111";
\U3|u1|add_rtl_4|adder|unreg_res_node[3]~I_modesel\ <= "1000001";
\U3|u1|add_rtl_4|adder|unreg_res_node[3]~I_pathsel\ <= "0000011000";
\U3|u1|s2[3]~I_modesel\ <= "1000001";
\U3|u1|s2[3]~I_pathsel\ <= "0000001000";
\U3|u1|process0~27_I_modesel\ <= "1000001";
\U3|u1|process0~27_I_pathsel\ <= "0000001110";
\U3|u1|c~I_modesel\ <= "1000001";
\U3|u1|c~I_pathsel\ <= "0000001110";
\U3|clkc1~I_modesel\ <= "1000001";
\U3|clkc1~I_pathsel\ <= "0000001111";
\U3|u2|s1[0]~I_modesel\ <= "1000001";
\U3|u2|s1[0]~I_pathsel\ <= "0000001000";
\U3|u2|s1[2]~I_modesel\ <= "1000001";
\U3|u2|s1[2]~I_pathsel\ <= "0000001110";
\U3|u2|s1[3]~I_modesel\ <= "1000001";
\U3|u2|s1[3]~I_pathsel\ <= "0000001111";
\U3|u2|s1[1]~I_modesel\ <= "1000001";
\U3|u2|s1[1]~I_pathsel\ <= "0000001111";
\U3|u2|Equal~40_I_modesel\ <= "1000001";
\U3|u2|Equal~40_I_pathsel\ <= "0000001111";
\U3|u2|add_rtl_7|adder|result_node|cs_buffer[0]~I_modesel\ <= "1000010";
\U3|u2|add_rtl_7|adder|result_node|cs_buffer[0]~I_pathsel\ <= "0011000011";
\U3|u2|s2[0]~I_modesel\ <= "1000001";
\U3|u2|s2[0]~I_pathsel\ <= "0000001000";
\U3|u2|add_rtl_7|adder|result_node|cs_buffer[1]~I_modesel\ <= "1000010";
\U3|u2|add_rtl_7|adder|result_node|cs_buffer[1]~I_pathsel\ <= "0110010010";
\U3|u2|s2[1]~I_modesel\ <= "1000001";
\U3|u2|s2[1]~I_pathsel\ <= "0000001111";
\U3|u2|add_rtl_7|adder|result_node|cs_buffer[2]~I_modesel\ <= "1000010";
\U3|u2|add_rtl_7|adder|result_node|cs_buffer[2]~I_pathsel\ <= "0110010010";
\U3|u2|s2[2]~I_modesel\ <= "1000001";
\U3|u2|s2[2]~I_pathsel\ <= "0000001111";
\U3|u2|add_rtl_7|adder|unreg_res_node[3]~I_modesel\ <= "1000001";
\U3|u2|add_rtl_7|adder|unreg_res_node[3]~I_pathsel\ <= "0000011000";
\U3|u2|s2[3]~I_modesel\ <= "1000001";
\U3|u2|s2[3]~I_pathsel\ <= "0000001000";
\U3|u2|process0~24_I_modesel\ <= "1000001";
\U3|u2|process0~24_I_pathsel\ <= "0000001110";
\U3|u2|c~I_modesel\ <= "1000001";
\U3|u2|c~I_pathsel\ <= "0000001110";
\U3|clkc2~I_modesel\ <= "1000001";
\U3|clkc2~I_pathsel\ <= "0000001111";
\U3|clkc3~I_modesel\ <= "1000001";
\U3|clkc3~I_pathsel\ <= "0000001111";
\U3|u3|s1_rtl_2|wysi_counter|q[0]~I_modesel\ <= "1001000";
\U3|u3|s1_rtl_2|wysi_counter|q[0]~I_pathsel\ <= "1000100000";
\U3|u3|s1_rtl_2|wysi_counter|q[1]~I_modesel\ <= "1001000";
\U3|u3|s1_rtl_2|wysi_counter|q[1]~I_pathsel\ <= "1000100000";
\U3|u3|s1_rtl_2|wysi_counter|q[2]~I_modesel\ <= "1001000";
\U3|u3|s1_rtl_2|wysi_counter|q[2]~I_pathsel\ <= "1000100000";
\U3|u3|s1_rtl_2|wysi_counter|q[3]~I_modesel\ <= "1001000";
\U3|u3|s1_rtl_2|wysi_counter|q[3]~I_pathsel\ <= "0000100000";
\U3|u3|Equal~48_I_modesel\ <= "1000001";
\U3|u3|Equal~48_I_pathsel\ <= "0000001100";
\U3|u3|s1~27_I_modesel\ <= "1000001";
\U3|u3|s1~27_I_pathsel\ <= "0000001111";
\U3|u3|process0~0_I_modesel\ <= "1000001";
\U3|u3|process0~0_I_pathsel\ <= "0000001111";
\U3|u3|add_rtl_10|adder|result_node|cs_buffer[0]~I_modesel\ <= "1000010";
\U3|u3|add_rtl_10|adder|result_node|cs_buffer[0]~I_pathsel\ <= "0011000011";
\U3|u3|s2[0]~I_modesel\ <= "1000001";
\U3|u3|s2[0]~I_pathsel\ <= "0000001000";
\U3|u3|add_rtl_10|adder|result_node|cs_buffer[1]~I_modesel\ <= "1000010";
\U3|u3|add_rtl_10|adder|result_node|cs_buffer[1]~I_pathsel\ <= "0110010010";
\U3|u3|s2[1]~I_modesel\ <= "1000001";
\U3|u3|s2[1]~I_pathsel\ <= "0000001100";
\U3|u3|add_rtl_10|adder|result_node|cs_buffer[2]~I_modesel\ <= "1000010";
\U3|u3|add_rtl_10|adder|result_node|cs_buffer[2]~I_pathsel\ <= "0110010010";
\U3|u3|s2[2]~I_modesel\ <= "1000001";
\U3|u3|s2[2]~I_pathsel\ <= "0000001000";
\U3|u3|process0~48_I_modesel\ <= "1000001";
\U3|u3|process0~48_I_pathsel\ <= "0000001111";
\U3|u3|c~I_modesel\ <= "1000001";
\U3|u3|c~I_pathsel\ <= "0000001111";
\U3|clkc4~I_modesel\ <= "1000001";
\U3|clkc4~I_pathsel\ <= "0000001111";
\U3|clkc5~I_modesel\ <= "1000001";
\U3|clkc5~I_pathsel\ <= "0000001111";
\U3|U4|s1[3]~I_modesel\ <= "1000001";
\U3|U4|s1[3]~I_pathsel\ <= "0000001110";
\U3|U4|s2~145_I_modesel\ <= "1000001";
\U3|U4|s2~145_I_pathsel\ <= "0000001111";
\U3|U4|s2~144_I_modesel\ <= "1000001";
\U3|U4|s2~144_I_pathsel\ <= "0000001111";
\U3|U4|s2~146_I_modesel\ <= "1000001";
\U3|U4|s2~146_I_pathsel\ <= "0000001111";
\U3|U4|s2_rtl_0|wysi_counter|q[0]~I_modesel\ <= "1001000";
\U3|U4|s2_rtl_0|wysi_counter|q[0]~I_pathsel\ <= "1000100001";
\U3|U4|s2_rtl_0|wysi_counter|q[1]~I_modesel\ <= "1001000";
\U3|U4|s2_rtl_0|wysi_counter|q[1]~I_pathsel\ <= "1000100001";
\U3|U4|s2_rtl_0|wysi_counter|q[2]~I_modesel\ <= "1001000";
\U3|U4|s2_rtl_0|wysi_counter|q[2]~I_pathsel\ <= "1000100001";
\U3|U4|s2_rtl_0|wysi_counter|q[3]~I_modesel\ <= "1001000";
\U3|U4|s2_rtl_0|wysi_counter|q[3]~I_pathsel\ <= "0000100001";
\U3|U4|Equal~240_I_modesel\ <= "1000001";
\U3|U4|Equal~240_I_pathsel\ <= "0000001111";
\U3|U4|add~75_I_modesel\ <= "1000001";
\U3|U4|add~75_I_pathsel\ <= "0000001110";
\U3|U4|s1[2]~I_modesel\ <= "1000001";
\U3|U4|s1[2]~I_pathsel\ <= "0000001111";
\U3|U4|Equal~23
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