clock.vho

功能更加完善的基于vhdl的数字时钟设计 有秒表

SIGNAL \U3|u3|add_rtl_10|adder|result_node|cout[0]\ : std_logic;
SIGNAL \U3|u3|add_rtl_10|adder|result_node|cs_buffer[1]\ : std_logic;
SIGNAL \U3|u3|s2[1]\ : std_logic;
SIGNAL \U3|u3|add_rtl_10|adder|result_node|cout[1]\ : std_logic;
SIGNAL \U3|u3|add_rtl_10|adder|result_node|cs_buffer[2]\ : std_logic;
SIGNAL \U3|u3|s2[2]\ : std_logic;
SIGNAL \U3|u3|process0~48\ : std_logic;
SIGNAL \U3|u3|c\ : std_logic;
SIGNAL \U3|clkc4\ : std_logic;
SIGNAL \U3|clkc5\ : std_logic;
SIGNAL \U3|U4|s1[3]\ : std_logic;
SIGNAL \U3|U4|s2~145\ : std_logic;
SIGNAL \U3|U4|s2~144\ : std_logic;
SIGNAL \U3|U4|s2~146\ : std_logic;
SIGNAL \U3|U4|s2_rtl_0|wysi_counter|counter_cell[0]~COUT\ : std_logic;
SIGNAL \U3|U4|s2_rtl_0|wysi_counter|counter_cell[1]~COUT\ : std_logic;
SIGNAL \U3|U4|s2_rtl_0|wysi_counter|counter_cell[2]~COUT\ : std_logic;
SIGNAL \U3|U4|s2_rtl_0|wysi_counter|q[3]\ : std_logic;
SIGNAL \U3|U4|s2_rtl_0|wysi_counter|q[1]\ : std_logic;
SIGNAL \U3|U4|Equal~240\ : std_logic;
SIGNAL \U3|U4|add~75\ : std_logic;
SIGNAL \U3|U4|s1[2]\ : std_logic;
SIGNAL \U3|U4|Equal~239\ : std_logic;
SIGNAL \U3|U4|process0~198\ : std_logic;
SIGNAL \U3|U4|process0~11\ : std_logic;
SIGNAL \U3|U4|c~343\ : std_logic;
SIGNAL \U3|U4|c~339\ : std_logic;
SIGNAL \U3|U4|c\ : std_logic;
SIGNAL \U3|clkc6\ : std_logic;
SIGNAL \U3|clkc7\ : std_logic;
SIGNAL \U3|u5|s1[0]\ : std_logic;
SIGNAL \U3|u5|s1[3]\ : std_logic;
SIGNAL \U3|u5|Equal~50\ : std_logic;
SIGNAL \U3|u5|s1[1]\ : std_logic;
SIGNAL \U3|u5|s1~120\ : std_logic;
SIGNAL \U3|u5|s1[2]\ : std_logic;
SIGNAL \U3|u5|add_rtl_11|adder|result_node|cs_buffer[0]\ : std_logic;
SIGNAL \U3|u5|s2[0]\ : std_logic;
SIGNAL \U3|u5|add_rtl_11|adder|result_node|cout[0]\ : std_logic;
SIGNAL \U3|u5|add_rtl_11|adder|result_node|cs_buffer[1]\ : std_logic;
SIGNAL \U3|u5|s2[1]\ : std_logic;
SIGNAL \U3|u5|add_rtl_11|adder|result_node|cout[1]\ : std_logic;
SIGNAL \U3|u5|add_rtl_11|adder|result_node|cs_buffer[2]\ : std_logic;
SIGNAL \U3|u5|s2[2]\ : std_logic;
SIGNAL \U3|u5|process0~72\ : std_logic;
SIGNAL \U3|u5|process0~69\ : std_logic;
SIGNAL \U3|u5|s3[1]\ : std_logic;
SIGNAL \U3|u5|s3[2]\ : std_logic;
SIGNAL \U3|U4|process0~216\ : std_logic;
SIGNAL \U3|U4|process0~207\ : std_logic;
SIGNAL \U3|U4|s1~813\ : std_logic;
SIGNAL \U3|U4|s1[0]\ : std_logic;
SIGNAL \U3|U4|s2_rtl_0|wysi_counter|q[0]\ : std_logic;
SIGNAL \U3|U4|process0~199\ : std_logic;
SIGNAL \U3|U4|s1~815\ : std_logic;
SIGNAL \U3|U4|s1[1]\ : std_logic;
SIGNAL \co1~1404\ : std_logic;
SIGNAL \U4|U1|s1[2]\ : std_logic;
SIGNAL \U4|U1|s1[3]\ : std_logic;
SIGNAL \U4|U1|s1[1]\ : std_logic;
SIGNAL \co1~1428\ : std_logic;
SIGNAL \co1~1413\ : std_logic;
SIGNAL \co1~1407\ : std_logic;
SIGNAL \co1~1432\ : std_logic;
SIGNAL \co1~1414\ : std_logic;
SIGNAL \co1~1410\ : std_logic;
SIGNAL \co1~1436\ : std_logic;
SIGNAL \co1~1415\ : std_logic;
SIGNAL \U2|u1|add_rtl_3|adder|result_node|cs_buffer[0]\ : std_logic;
SIGNAL \U2|u1|s2[0]\ : std_logic;
SIGNAL \co2~1341\ : std_logic;
SIGNAL \U4|U1|add_rtl_5|adder|result_node|cs_buffer[0]\ : std_logic;
SIGNAL \U4|U1|s2[0]\ : std_logic;
SIGNAL \co2~1361\ : std_logic;
SIGNAL \co2~1352\ : std_logic;
SIGNAL \U2|u1|add_rtl_3|adder|result_node|cout[0]\ : std_logic;
SIGNAL \U2|u1|add_rtl_3|adder|result_node|cout[1]\ : std_logic;
SIGNAL \U2|u1|add_rtl_3|adder|result_node|cs_buffer[2]\ : std_logic;
SIGNAL \U2|u1|s2[2]\ : std_logic;
SIGNAL \U2|u1|add_rtl_3|adder|result_node|cout[2]\ : std_logic;
SIGNAL \U2|u1|add_rtl_3|adder|unreg_res_node[3]\ : std_logic;
SIGNAL \U2|u1|s2[3]\ : std_logic;
SIGNAL \U2|u1|process0~24\ : std_logic;
SIGNAL \U2|u1|process0~0\ : std_logic;
SIGNAL \U2|u1|add_rtl_3|adder|result_node|cs_buffer[1]\ : std_logic;
SIGNAL \U2|u1|s2[1]\ : std_logic;
SIGNAL \co2~1344\ : std_logic;
SIGNAL \U4|U1|Equal~40\ : std_logic;
SIGNAL \U4|U1|add_rtl_5|adder|result_node|cout[0]\ : std_logic;
SIGNAL \U4|U1|add_rtl_5|adder|result_node|cs_buffer[1]\ : std_logic;
SIGNAL \U4|U1|s2[1]\ : std_logic;
SIGNAL \co2~1365\ : std_logic;
SIGNAL \co2~1353\ : std_logic;
SIGNAL \U3|U4|s2_rtl_0|wysi_counter|q[2]\ : std_logic;
SIGNAL \co2~1347\ : std_logic;
SIGNAL \U4|U1|add_rtl_5|adder|result_node|cout[1]\ : std_logic;
SIGNAL \U4|U1|add_rtl_5|adder|result_node|cs_buffer[2]\ : std_logic;
SIGNAL \U4|U1|s2[2]\ : std_logic;
SIGNAL \co2~1369\ : std_logic;
SIGNAL \co2~1354\ : std_logic;
SIGNAL \co2~1350\ : std_logic;
SIGNAL \U4|U1|add_rtl_5|adder|result_node|cout[2]\ : std_logic;
SIGNAL \U4|U1|add_rtl_5|adder|unreg_res_node[3]\ : std_logic;
SIGNAL \U4|U1|s2[3]\ : std_logic;
SIGNAL \co2~1373\ : std_logic;
SIGNAL \co2~1355\ : std_logic;
SIGNAL \schour~8\ : std_logic;
SIGNAL \U4|U2|s1_rtl_1|wysi_counter|counter_cell[0]~COUT\ : std_logic;
SIGNAL \U4|U2|s1_rtl_1|wysi_counter|counter_cell[1]~COUT\ : std_logic;
SIGNAL \U4|U2|s1_rtl_1|wysi_counter|counter_cell[2]~COUT\ : std_logic;
SIGNAL \U4|U2|s1_rtl_1|wysi_counter|q[3]\ : std_logic;
SIGNAL \U4|U2|s1_rtl_1|wysi_counter|q[1]\ : std_logic;
SIGNAL \U4|U2|s1_rtl_1|wysi_counter|q[2]\ : std_logic;
SIGNAL \U4|U2|Equal~48\ : std_logic;
SIGNAL \U4|U2|process0~0\ : std_logic;
SIGNAL \U4|U2|add_rtl_8|adder|result_node|cs_buffer[0]\ : std_logic;
SIGNAL \U4|U2|s2[0]\ : std_logic;
SIGNAL \U4|U2|add_rtl_8|adder|result_node|cout[0]\ : std_logic;
SIGNAL \U4|U2|add_rtl_8|adder|result_node|cs_buffer[1]\ : std_logic;
SIGNAL \U4|U2|s2[1]\ : std_logic;
SIGNAL \U4|U2|add_rtl_8|adder|result_node|cout[1]\ : std_logic;
SIGNAL \U4|U2|add_rtl_8|adder|result_node|cs_buffer[2]\ : std_logic;
SIGNAL \U4|U2|s2[2]\ : std_logic;
SIGNAL \U4|U2|process0~48\ : std_logic;
SIGNAL \U4|U2|s1~27\ : std_logic;
SIGNAL \U4|U2|s1_rtl_1|wysi_counter|q[0]\ : std_logic;
SIGNAL \co3~720\ : std_logic;
SIGNAL \U2|u1|c\ : std_logic;
SIGNAL \U2|u2|s1[0]\ : std_logic;
SIGNAL \co3~721\ : std_logic;
SIGNAL \co3~722\ : std_logic;
SIGNAL \U2|u2|s1[2]\ : std_logic;
SIGNAL \U2|u2|s1~74\ : std_logic;
SIGNAL \U2|u2|s1[3]\ : std_logic;
SIGNAL \U2|u2|Equal~40\ : std_logic;
SIGNAL \U2|u2|s1[1]\ : std_logic;
SIGNAL \co3~723\ : std_logic;
SIGNAL \co3~724\ : std_logic;
SIGNAL \co3~725\ : std_logic;
SIGNAL \co3~726\ : std_logic;
SIGNAL \co3~727\ : std_logic;
SIGNAL \co3~728\ : std_logic;
SIGNAL \U2|u2|add_rtl_6|adder|result_node|cs_buffer[0]\ : std_logic;
SIGNAL \U2|u2|s2[0]\ : std_logic;
SIGNAL \co4~716\ : std_logic;
SIGNAL \co4~717\ : std_logic;
SIGNAL \U2|u2|add_rtl_6|adder|result_node|cout[0]\ : std_logic;
SIGNAL \U2|u2|add_rtl_6|adder|result_node|cout[1]\ : std_logic;
SIGNAL \U2|u2|add_rtl_6|adder|result_node|cs_buffer[2]\ : std_logic;
SIGNAL \U2|u2|s2[2]\ : std_logic;
SIGNAL \U2|u2|add_rtl_6|adder|result_node|cout[2]\ : std_logic;
SIGNAL \U2|u2|add_rtl_6|adder|unreg_res_node[3]\ : std_logic;
SIGNAL \U2|u2|s2[3]\ : std_logic;
SIGNAL \U2|u2|process0~24\ : std_logic;
SIGNAL \U2|u2|process0~0\ : std_logic;
SIGNAL \U2|u2|add_rtl_6|adder|result_node|cs_buffer[1]\ : std_logic;
SIGNAL \U2|u2|s2[1]\ : std_logic;
SIGNAL \co4~718\ : std_logic;
SIGNAL \co4~719\ : std_logic;
SIGNAL \co4~720\ : std_logic;
SIGNAL \co4~721\ : std_logic;
SIGNAL \U4|U2|add_rtl_8|adder|result_node|cout[2]\ : std_logic;
SIGNAL \U4|U2|add_rtl_8|adder|unreg_res_node[3]\ : std_logic;
SIGNAL \U4|U2|s2[3]\ : std_logic;
SIGNAL \co4~722\ : std_logic;
SIGNAL \co4~723\ : std_logic;
SIGNAL \U2|u2|c\ : std_logic;
SIGNAL \U2|u3|s1[0]\ : std_logic;
SIGNAL \co5~670\ : std_logic;
SIGNAL \co5~671\ : std_logic;
SIGNAL \U2|u3|s1[2]\ : std_logic;
SIGNAL \U2|u3|s1~74\ : std_logic;
SIGNAL \U2|u3|s1[3]\ : std_logic;
SIGNAL \U2|u3|Equal~40\ : std_logic;
SIGNAL \U2|u3|s1[1]\ : std_logic;
SIGNAL \co5~672\ : std_logic;
SIGNAL \co5~673\ : std_logic;
SIGNAL \co5~674\ : std_logic;
SIGNAL \co5~675\ : std_logic;
SIGNAL \co5~676\ : std_logic;
SIGNAL \co5~677\ : std_logic;
SIGNAL \U2|u3|add_rtl_9|adder|result_node|cs_buffer[0]\ : std_logic;
SIGNAL \U2|u3|s2[0]\ : std_logic;
SIGNAL \co6~668\ : std_logic;
SIGNAL \co6~669\ : std_logic;
SIGNAL \U2|u3|add_rtl_9|adder|result_node|cout[0]\ : std_logic;
SIGNAL \U2|u3|add_rtl_9|adder|result_node|cout[1]\ : std_logic;
SIGNAL \U2|u3|add_rtl_9|adder|result_node|cs_buffer[2]\ : std_logic;
SIGNAL \U2|u3|s2[2]\ : std_logic;
SIGNAL \U2|u3|add_rtl_9|adder|result_node|cout[2]\ : std_logic;
SIGNAL \U2|u3|add_rtl_9|adder|unreg_res_node[3]\ : std_logic;
SIGNAL \U2|u3|s2[3]\ : std_logic;
SIGNAL \U2|u3|process0~24\ : std_logic;
SIGNAL \U2|u3|process0~0\ : std_logic;
SIGNAL \U2|u3|add_rtl_9|adder|result_node|cs_buffer[1]\ : std_logic;
SIGNAL \U2|u3|s2[1]\ : std_logic;
SIGNAL \co6~670\ : std_logic;
SIGNAL \co6~671\ : std_logic;
SIGNAL \co6~672\ : std_logic;
SIGNAL \co6~673\ : std_logic;
SIGNAL \U3|u5|add_rtl_11|adder|result_node|cout[2]\ : std_logic;
SIGNAL \U3|u5|add_rtl_11|adder|unreg_res_node[3]\ : std_logic;
SIGNAL \U3|u5|s2[3]\ : std_logic;
SIGNAL \U3|u3|add_rtl_10|adder|result_node|cout[2]\ : std_logic;
SIGNAL \U3|u3|add_rtl_10|adder|unreg_res_node[3]\ : std_logic;
SIGNAL \U3|u3|s2[3]\ : std_logic;
SIGNAL \co6~674\ : std_logic;
SIGNAL \co6~675\ : std_logic;
SIGNAL \c1~54\ : std_logic;
SIGNAL \c2~63\ : std_logic;
SIGNAL \c3~124\ : std_logic;
SIGNAL \ALT_INV_co1~1412\ : std_logic;
SIGNAL \ALT_INV_co1~1413\ : std_logic;
SIGNAL \ALT_INV_co1~1414\ : std_logic;
SIGNAL \ALT_INV_co1~1415\ : std_logic;
SIGNAL \ALT_INV_co2~1352\ : std_logic;
SIGNAL \ALT_INV_co2~1353\ : std_logic;
SIGNAL \ALT_INV_co2~1354\ : std_logic;
SIGNAL \ALT_INV_co2~1355\ : std_logic;
COMPONENT flex10ke_lcell
PORT (
	dataa : IN STD_LOGIC;
	datab : IN STD_LOGIC;
	datac : IN STD_LOGIC;
	datad : IN STD_LOGIC;
	aclr : IN STD_LOGIC;
	aload : IN STD_LOGIC;
	clk : IN STD_LOGIC;
	cin : IN STD_LOGIC;
	cascin : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	regout : OUT STD_LOGIC;
	cout : OUT STD_LOGIC;
	cascout : OUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
	pathsel : IN STD_LOGIC_VECTOR(9 DOWNTO 0));
END COMPONENT;

COMPONENT flex10ke_io
PORT (
	datain : IN STD_LOGIC;
	clk : IN STD_LOGIC;
	ena : IN STD_LOGIC;
	aclr : IN STD_LOGIC;
	oe : IN STD_LOGIC;
	dataout : OUT STD_LOGIC;
	padio : INOUT STD_LOGIC;