clock.vho

功能更加完善的基于vhdl的数字时钟设计 有秒表

SIGNAL \co4~717_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u2|add_rtl_6|adder|result_node|cs_buffer[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u2|add_rtl_6|adder|result_node|cs_buffer[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u2|add_rtl_6|adder|result_node|cs_buffer[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u2|add_rtl_6|adder|result_node|cs_buffer[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u2|s2[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u2|s2[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u2|add_rtl_6|adder|unreg_res_node[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u2|add_rtl_6|adder|unreg_res_node[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u2|s2[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u2|s2[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u2|process0~24_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u2|process0~24_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u2|process0~0_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u2|process0~0_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u2|s2[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u2|s2[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co4~718_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co4~718_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co4~719_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co4~719_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co4~720_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co4~720_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co4~721_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co4~721_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U2|add_rtl_8|adder|unreg_res_node[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U2|add_rtl_8|adder|unreg_res_node[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U2|s2[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U2|s2[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co4~722_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co4~722_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co4~723_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co4~723_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u2|c~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u2|c~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u3|s1[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u3|s1[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co5~670_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co5~670_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co5~671_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co5~671_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u3|s1[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u3|s1[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u3|s1~74_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u3|s1~74_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u3|s1[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u3|s1[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u3|Equal~40_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u3|Equal~40_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u3|s1[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u3|s1[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co5~672_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co5~672_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co5~673_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co5~673_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co5~674_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co5~674_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co5~675_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co5~675_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co5~676_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co5~676_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co5~677_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co5~677_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u3|add_rtl_9|adder|result_node|cs_buffer[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u3|add_rtl_9|adder|result_node|cs_buffer[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u3|s2[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u3|s2[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co6~668_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co6~668_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co6~669_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co6~669_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u3|add_rtl_9|adder|result_node|cs_buffer[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u3|add_rtl_9|adder|result_node|cs_buffer[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u3|add_rtl_9|adder|result_node|cs_buffer[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u3|add_rtl_9|adder|result_node|cs_buffer[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u3|s2[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u3|s2[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u3|add_rtl_9|adder|unreg_res_node[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u3|add_rtl_9|adder|unreg_res_node[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u3|s2[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u3|s2[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u3|process0~24_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u3|process0~24_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u3|process0~0_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u3|process0~0_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u3|s2[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u3|s2[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co6~670_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co6~670_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co6~671_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co6~671_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co6~672_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co6~672_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co6~673_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co6~673_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u5|add_rtl_11|adder|unreg_res_node[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u5|add_rtl_11|adder|unreg_res_node[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u5|s2[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u5|s2[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u3|add_rtl_10|adder|unreg_res_node[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u3|add_rtl_10|adder|unreg_res_node[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u3|s2[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u3|s2[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co6~674_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co6~674_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co6~675_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co6~675_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \c1~54_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \c1~54_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \c2~63_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \c2~63_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \c3~124_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \c3~124_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co1[0]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \co1[1]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \co1[2]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \co1[3]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \co2[0]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \co2[1]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \co2[2]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \co2[3]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \co3[0]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \co3[1]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \co3[2]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \co3[3]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \co4[0]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \co4[1]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \co4[2]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \co4[3]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \co5[0]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \co5[1]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \co5[2]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \co5[3]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \co6[0]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \co6[1]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \co6[2]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \co6[3]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \c1~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \c2~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \c3~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \U3|u5|add~143\ : std_logic;
SIGNAL \co1~1400\ : std_logic;
SIGNAL \co1~1403\ : std_logic;
SIGNAL \co1~1406\ : std_logic;
SIGNAL \co1~1409\ : std_logic;
SIGNAL \co2~1340\ : std_logic;
SIGNAL \co2~1343\ : std_logic;
SIGNAL \co2~1346\ : std_logic;
SIGNAL \co2~1349\ : std_logic;
SIGNAL \U3|u5|s3[3]\ : std_logic;
SIGNAL \U3|U4|process0~200\ : std_logic;
SIGNAL \U4|U1|process0~24\ : std_logic;
SIGNAL \U2|u1|c~0\ : std_logic;
SIGNAL \U4|U2|Equal~49\ : std_logic;
SIGNAL \U3|u5|process0~67\ : std_logic;
SIGNAL \U3|u3|Equal~49\ : std_logic;
SIGNAL \U3|u5|Equal~51\ : std_logic;
SIGNAL \U3|u5|add~144\ : std_logic;
SIGNAL \U3|U4|c~336\ : std_logic;
SIGNAL \U3|U4|process0~206\ : std_logic;
SIGNAL \U3|U4|c~338\ : std_logic;
SIGNAL \set~dataout\ : std_logic;
SIGNAL \U1|c[0]\ : std_logic;
SIGNAL \U1|c[1]\ : std_logic;
SIGNAL \U1|c[2]\ : std_logic;
SIGNAL \clo~dataout\ : std_logic;
SIGNAL cecl : std_logic;
SIGNAL \cnt[0]\ : std_logic;
SIGNAL \U1|sday~88\ : std_logic;
SIGNAL \date~dataout\ : std_logic;
SIGNAL \clk~dataout\ : std_logic;
SIGNAL ced : std_logic;
SIGNAL \U2|u1|s1[0]\ : std_logic;
SIGNAL \co1~1387\ : std_logic;
SIGNAL \process2~4\ : std_logic;
SIGNAL \co1~1386\ : std_logic;
SIGNAL \U3|u1|s1[0]\ : std_logic;
SIGNAL \co1~1401\ : std_logic;
SIGNAL \co1~1385\ : std_logic;
SIGNAL \scmin~9\ : std_logic;
SIGNAL \U4|U1|s1[0]\ : std_logic;
SIGNAL \co1~1424\ : std_logic;
SIGNAL \co1~1412\ : std_logic;
SIGNAL \U2|u1|s1[2]\ : std_logic;
SIGNAL \U2|u1|s1~74\ : std_logic;
SIGNAL \U2|u1|s1[3]\ : std_logic;
SIGNAL \U2|u1|Equal~40\ : std_logic;
SIGNAL \U2|u1|s1[1]\ : std_logic;
SIGNAL \U3|u1|s1[2]\ : std_logic;
SIGNAL \U3|u1|s1[3]\ : std_logic;
SIGNAL \U3|u1|s1[1]\ : std_logic;
SIGNAL \rst~dataout\ : std_logic;
SIGNAL \smon~2\ : std_logic;
SIGNAL \U3|u5|s3[0]\ : std_logic;
SIGNAL \U3|U4|Equal~238\ : std_logic;
SIGNAL \U3|U4|process0~204\ : std_logic;
SIGNAL \U3|U4|Equal~237\ : std_logic;
SIGNAL \U3|U4|s1~816\ : std_logic;
SIGNAL \U3|U4|s1~819\ : std_logic;
SIGNAL \process2~80\ : std_logic;
SIGNAL \U3|u1|Equal~40\ : std_logic;
SIGNAL \U3|u1|add_rtl_4|adder|result_node|cs_buffer[0]\ : std_logic;
SIGNAL \U3|u1|s2[0]\ : std_logic;
SIGNAL \U3|u1|add_rtl_4|adder|result_node|cout[0]\ : std_logic;
SIGNAL \U3|u1|add_rtl_4|adder|result_node|cs_buffer[1]\ : std_logic;
SIGNAL \U3|u1|s2[1]\ : std_logic;
SIGNAL \U3|u1|add_rtl_4|adder|result_node|cout[1]\ : std_logic;
SIGNAL \U3|u1|add_rtl_4|adder|result_node|cs_buffer[2]\ : std_logic;
SIGNAL \U3|u1|s2[2]\ : std_logic;
SIGNAL \U3|u1|add_rtl_4|adder|result_node|cout[2]\ : std_logic;
SIGNAL \U3|u1|add_rtl_4|adder|unreg_res_node[3]\ : std_logic;
SIGNAL \U3|u1|s2[3]\ : std_logic;
SIGNAL \U3|u1|process0~27\ : std_logic;
SIGNAL \U3|u1|c\ : std_logic;
SIGNAL \U3|clkc1\ : std_logic;
SIGNAL \U3|u2|s1[0]\ : std_logic;
SIGNAL \U3|u2|s1[2]\ : std_logic;
SIGNAL \U3|u2|s1[3]\ : std_logic;
SIGNAL \U3|u2|s1[1]\ : std_logic;
SIGNAL \U3|u2|Equal~40\ : std_logic;
SIGNAL \U3|u2|add_rtl_7|adder|result_node|cs_buffer[0]\ : std_logic;
SIGNAL \U3|u2|s2[0]\ : std_logic;
SIGNAL \U3|u2|add_rtl_7|adder|result_node|cout[0]\ : std_logic;
SIGNAL \U3|u2|add_rtl_7|adder|result_node|cs_buffer[1]\ : std_logic;
SIGNAL \U3|u2|s2[1]\ : std_logic;
SIGNAL \U3|u2|add_rtl_7|adder|result_node|cout[1]\ : std_logic;
SIGNAL \U3|u2|add_rtl_7|adder|result_node|cs_buffer[2]\ : std_logic;
SIGNAL \U3|u2|s2[2]\ : std_logic;
SIGNAL \U3|u2|add_rtl_7|adder|result_node|cout[2]\ : std_logic;
SIGNAL \U3|u2|add_rtl_7|adder|unreg_res_node[3]\ : std_logic;
SIGNAL \U3|u2|s2[3]\ : std_logic;
SIGNAL \U3|u2|process0~24\ : std_logic;
SIGNAL \U3|u2|c\ : std_logic;
SIGNAL \U3|clkc2\ : std_logic;
SIGNAL \U3|clkc3\ : std_logic;
SIGNAL \U3|u3|s1_rtl_2|wysi_counter|counter_cell[0]~COUT\ : std_logic;
SIGNAL \U3|u3|s1_rtl_2|wysi_counter|counter_cell[1]~COUT\ : std_logic;
SIGNAL \U3|u3|s1_rtl_2|wysi_counter|counter_cell[2]~COUT\ : std_logic;
SIGNAL \U3|u3|s1_rtl_2|wysi_counter|q[3]\ : std_logic;
SIGNAL \U3|u3|s1_rtl_2|wysi_counter|q[2]\ : std_logic;
SIGNAL \U3|u3|s1_rtl_2|wysi_counter|q[0]\ : std_logic;
SIGNAL \U3|u3|Equal~48\ : std_logic;
SIGNAL \U3|u3|s1~27\ : std_logic;
SIGNAL \U3|u3|s1_rtl_2|wysi_counter|q[1]\ : std_logic;
SIGNAL \U3|u3|process0~0\ : std_logic;
SIGNAL \U3|u3|add_rtl_10|adder|result_node|cs_buffer[0]\ : std_logic;
SIGNAL \U3|u3|s2[0]\ : std_logic;