⭐ 欢迎来到虫虫下载站！ | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站
📤 上传资源

📄 clock.vho

📁 功能更加完善的基于vhdl的数字时钟设计 有秒表
💻 VHO
📖 第 1 页 / 共 5 页
字号:
🔍
12345 
SIGNAL \U3|u3|process0~48_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u3|process0~48_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u3|c~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u3|c~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|clkc4~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|clkc4~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|clkc5~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|clkc5~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|s1[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|s1[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|s2~145_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|s2~145_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|s2~144_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|s2~144_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|s2~146_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|s2~146_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|s2_rtl_0|wysi_counter|q[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|s2_rtl_0|wysi_counter|q[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|s2_rtl_0|wysi_counter|q[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|s2_rtl_0|wysi_counter|q[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|s2_rtl_0|wysi_counter|q[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|s2_rtl_0|wysi_counter|q[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|s2_rtl_0|wysi_counter|q[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|s2_rtl_0|wysi_counter|q[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|Equal~240_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|Equal~240_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|add~75_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|add~75_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|s1[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|s1[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|Equal~239_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|Equal~239_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|process0~198_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|process0~198_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|process0~11_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|process0~11_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|c~336_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|c~336_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|c~339_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|c~339_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|c~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|c~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|clkc6~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|clkc6~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|clkc7~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|clkc7~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u5|s1[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u5|s1[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u5|s1[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u5|s1[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u5|Equal~50_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u5|Equal~50_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u5|s1[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u5|s1[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u5|s1~120_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u5|s1~120_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u5|s1[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u5|s1[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u5|add_rtl_11|adder|result_node|cs_buffer[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u5|add_rtl_11|adder|result_node|cs_buffer[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u5|s2[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u5|s2[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u5|add_rtl_11|adder|result_node|cs_buffer[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u5|add_rtl_11|adder|result_node|cs_buffer[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u5|s2[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u5|s2[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u5|add_rtl_11|adder|result_node|cs_buffer[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u5|add_rtl_11|adder|result_node|cs_buffer[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u5|s2[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u5|s2[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u5|process0~67_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u5|process0~67_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u5|process0~69_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u5|process0~69_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u5|s3[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u5|s3[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u5|s3[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u5|s3[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|process0~206_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|process0~206_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|process0~207_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|process0~207_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|s1~813_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|s1~813_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|s1[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|s1[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|process0~199_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|process0~199_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|s1~815_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|s1~815_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|s1[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|s1[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co1~1404_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co1~1404_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U1|s1[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U1|s1[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U1|s1[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U1|s1[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U1|s1[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U1|s1[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co1~1403_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co1~1403_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co1~1413_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co1~1413_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co1~1407_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co1~1407_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co1~1406_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co1~1406_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co1~1414_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co1~1414_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co1~1410_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co1~1410_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co1~1409_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co1~1409_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co1~1415_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co1~1415_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u1|add_rtl_3|adder|result_node|cs_buffer[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u1|add_rtl_3|adder|result_node|cs_buffer[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u1|s2[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u1|s2[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co2~1341_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co2~1341_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U1|add_rtl_5|adder|result_node|cs_buffer[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U1|add_rtl_5|adder|result_node|cs_buffer[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U1|s2[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U1|s2[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co2~1340_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co2~1340_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co2~1352_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co2~1352_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u1|add_rtl_3|adder|result_node|cs_buffer[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u1|add_rtl_3|adder|result_node|cs_buffer[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u1|add_rtl_3|adder|result_node|cs_buffer[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u1|add_rtl_3|adder|result_node|cs_buffer[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u1|s2[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u1|s2[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u1|add_rtl_3|adder|unreg_res_node[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u1|add_rtl_3|adder|unreg_res_node[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u1|s2[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u1|s2[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u1|process0~24_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u1|process0~24_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u1|process0~0_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u1|process0~0_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u1|s2[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u1|s2[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co2~1344_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co2~1344_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U1|Equal~40_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U1|Equal~40_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U1|add_rtl_5|adder|result_node|cs_buffer[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U1|add_rtl_5|adder|result_node|cs_buffer[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U1|s2[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U1|s2[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co2~1343_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co2~1343_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co2~1353_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co2~1353_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co2~1347_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co2~1347_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U1|add_rtl_5|adder|result_node|cs_buffer[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U1|add_rtl_5|adder|result_node|cs_buffer[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U1|s2[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U1|s2[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co2~1346_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co2~1346_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co2~1354_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co2~1354_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co2~1350_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co2~1350_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U1|add_rtl_5|adder|unreg_res_node[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U1|add_rtl_5|adder|unreg_res_node[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U1|s2[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U1|s2[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co2~1349_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co2~1349_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co2~1355_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co2~1355_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \schour~8_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \schour~8_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U2|s1_rtl_1|wysi_counter|q[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U2|s1_rtl_1|wysi_counter|q[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U2|s1_rtl_1|wysi_counter|q[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U2|s1_rtl_1|wysi_counter|q[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U2|s1_rtl_1|wysi_counter|q[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U2|s1_rtl_1|wysi_counter|q[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U2|s1_rtl_1|wysi_counter|q[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U2|s1_rtl_1|wysi_counter|q[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U2|Equal~48_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U2|Equal~48_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U2|process0~0_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U2|process0~0_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U2|add_rtl_8|adder|result_node|cs_buffer[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U2|add_rtl_8|adder|result_node|cs_buffer[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U2|s2[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U2|s2[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U2|add_rtl_8|adder|result_node|cs_buffer[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U2|add_rtl_8|adder|result_node|cs_buffer[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U2|s2[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U2|s2[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U2|add_rtl_8|adder|result_node|cs_buffer[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U2|add_rtl_8|adder|result_node|cs_buffer[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U2|s2[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U2|s2[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U2|process0~48_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U2|process0~48_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U2|s1~27_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U2|s1~27_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co3~720_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co3~720_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u1|c~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u1|c~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u2|s1[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u2|s1[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co3~721_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co3~721_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co3~722_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co3~722_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u2|s1[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u2|s1[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u2|s1~74_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u2|s1~74_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u2|s1[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u2|s1[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u2|Equal~40_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u2|Equal~40_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u2|s1[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u2|s1[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co3~723_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co3~723_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co3~724_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co3~724_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co3~725_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co3~725_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co3~726_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co3~726_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co3~727_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co3~727_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co3~728_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co3~728_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u2|add_rtl_6|adder|result_node|cs_buffer[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u2|add_rtl_6|adder|result_node|cs_buffer[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u2|s2[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u2|s2[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co4~716_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co4~716_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co4~717_I_modesel\ : std_logic_vector(6 DOWNTO 0);
12345

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -