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📄 clock.vho

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-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version"

-- DATE "12/08/2007 19:12:14"

-- 
-- Device: Altera EP1K10TC144-3 Package TQFP144
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	clock IS
    PORT (
	set : IN std_logic;
	date : IN std_logic;
	clo : IN std_logic;
	clk : IN std_logic;
	rst : IN std_logic;
	co1 : OUT std_logic_vector(3 DOWNTO 0);
	co2 : OUT std_logic_vector(3 DOWNTO 0);
	co3 : OUT std_logic_vector(3 DOWNTO 0);
	co4 : OUT std_logic_vector(3 DOWNTO 0);
	co5 : OUT std_logic_vector(3 DOWNTO 0);
	co6 : OUT std_logic_vector(3 DOWNTO 0);
	c1 : OUT std_logic;
	c2 : OUT std_logic;
	c3 : OUT std_logic
	);
END clock;

ARCHITECTURE structure OF clock IS
SIGNAL GNDs : std_logic_vector(1024 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(1024 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL lcell_ff_enable_asynch_arcs_out : std_logic;
SIGNAL ww_set : std_logic;
SIGNAL ww_date : std_logic;
SIGNAL ww_clo : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_rst : std_logic;
SIGNAL ww_co1 : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_co2 : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_co3 : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_co4 : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_co5 : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_co6 : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_c1 : std_logic;
SIGNAL ww_c2 : std_logic;
SIGNAL ww_c3 : std_logic;
SIGNAL \U3|u5|add~143_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u5|add~143_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u5|s3[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u5|s3[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|process0~200_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|process0~200_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U1|process0~24_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U1|process0~24_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u1|c~0_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u1|c~0_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U2|Equal~49_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U2|Equal~49_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u3|Equal~49_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u3|Equal~49_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u5|Equal~51_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u5|Equal~51_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u5|add~144_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u5|add~144_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|c~338_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|c~338_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \set~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \U1|c[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U1|c[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U1|c[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U1|c[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U1|c[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U1|c[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \clo~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \cecl~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cecl~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cnt[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cnt[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U1|sday~88_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U1|sday~88_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \date~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \ced~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ced~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u1|s1[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u1|s1[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co1~1387_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co1~1387_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \process2~4_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \process2~4_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co1~1386_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co1~1386_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u1|s1[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u1|s1[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co1~1401_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co1~1401_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co1~1385_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co1~1385_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \scmin~9_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \scmin~9_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U4|U1|s1[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U4|U1|s1[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co1~1400_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co1~1400_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \co1~1412_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \co1~1412_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u1|s1[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u1|s1[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u1|s1~74_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u1|s1~74_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u1|s1[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u1|s1[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u1|Equal~40_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u1|Equal~40_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|u1|s1[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U2|u1|s1[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u1|s1[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u1|s1[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u1|s1[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u1|s1[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u1|s1[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u1|s1[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \rst~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \smon~2_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \smon~2_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u5|s3[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u5|s3[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|Equal~238_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|Equal~238_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|process0~204_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|process0~204_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|Equal~237_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|Equal~237_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|s1~816_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|s1~816_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|U4|s1~819_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|U4|s1~819_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \process2~80_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \process2~80_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u1|Equal~40_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u1|Equal~40_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u1|add_rtl_4|adder|result_node|cs_buffer[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u1|add_rtl_4|adder|result_node|cs_buffer[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u1|s2[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u1|s2[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u1|add_rtl_4|adder|result_node|cs_buffer[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u1|add_rtl_4|adder|result_node|cs_buffer[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u1|s2[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u1|s2[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u1|add_rtl_4|adder|result_node|cs_buffer[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u1|add_rtl_4|adder|result_node|cs_buffer[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u1|s2[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u1|s2[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u1|add_rtl_4|adder|unreg_res_node[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u1|add_rtl_4|adder|unreg_res_node[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u1|s2[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u1|s2[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u1|process0~27_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u1|process0~27_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u1|c~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u1|c~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|clkc1~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|clkc1~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u2|s1[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u2|s1[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u2|s1[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u2|s1[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u2|s1[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u2|s1[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u2|s1[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u2|s1[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u2|Equal~40_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u2|Equal~40_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u2|add_rtl_7|adder|result_node|cs_buffer[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u2|add_rtl_7|adder|result_node|cs_buffer[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u2|s2[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u2|s2[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u2|add_rtl_7|adder|result_node|cs_buffer[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u2|add_rtl_7|adder|result_node|cs_buffer[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u2|s2[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u2|s2[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u2|add_rtl_7|adder|result_node|cs_buffer[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u2|add_rtl_7|adder|result_node|cs_buffer[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u2|s2[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u2|s2[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u2|add_rtl_7|adder|unreg_res_node[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u2|add_rtl_7|adder|unreg_res_node[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u2|s2[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u2|s2[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u2|process0~24_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u2|process0~24_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u2|c~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u2|c~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|clkc2~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|clkc2~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|clkc3~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|clkc3~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u3|s1_rtl_2|wysi_counter|q[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u3|s1_rtl_2|wysi_counter|q[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u3|s1_rtl_2|wysi_counter|q[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u3|s1_rtl_2|wysi_counter|q[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u3|s1_rtl_2|wysi_counter|q[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u3|s1_rtl_2|wysi_counter|q[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u3|s1_rtl_2|wysi_counter|q[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u3|s1_rtl_2|wysi_counter|q[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u3|Equal~48_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u3|Equal~48_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u3|s1~27_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u3|s1~27_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u3|process0~0_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u3|process0~0_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u3|add_rtl_10|adder|result_node|cs_buffer[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u3|add_rtl_10|adder|result_node|cs_buffer[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u3|s2[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u3|s2[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u3|add_rtl_10|adder|result_node|cs_buffer[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u3|add_rtl_10|adder|result_node|cs_buffer[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u3|s2[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u3|s2[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u3|add_rtl_10|adder|result_node|cs_buffer[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u3|add_rtl_10|adder|result_node|cs_buffer[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U3|u3|s2[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \U3|u3|s2[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
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