clock.flow.rpt

功能更加完善的基于vhdl的数字时钟设计 有秒表

Flow report for clock
Sat Dec 08 19:12:14 2007
Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Elapsed Time
  5. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------+
; Flow Summary                                                            ;
+-------------------------+-----------------------------------------------+
; Flow Status             ; Successful - Sat Dec 08 19:12:14 2007         ;
; Quartus II Version      ; 5.1 Build 216 03/06/2006 SP 2 SJ Full Version ;
; Revision Name           ; clock                                         ;
; Top-level Entity Name   ; clock                                         ;
; Family                  ; ACEX1K                                        ;
; Device                  ; EP1K10TC144-3                                 ;
; Timing Models           ; Final                                         ;
; Met timing requirements ; No                                            ;
; Total logic elements    ; 266 / 576 ( 46 % )                            ;
; Total pins              ; 32 / 92 ( 35 % )                              ;
; Total memory bits       ; 0 / 12,288 ( 0 % )                            ;
; Total PLLs              ; 0                                             ;
+-------------------------+-----------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 12/08/2007 19:11:52 ;
; Main task         ; Compilation         ;
; Revision Name     ; clock               ;
+-------------------+---------------------+


+-------------------------------------+
; Flow Elapsed Time                   ;
+----------------------+--------------+
; Module Name          ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:07     ;
; Fitter               ; 00:00:07     ;
; Assembler            ; 00:00:01     ;
; Timing Analyzer      ; 00:00:02     ;
; EDA Netlist Writer   ; 00:00:02     ;
; Total                ; 00:00:19     ;
+----------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off clock -c clock
quartus_fit --read_settings_files=off --write_settings_files=off clock -c clock
quartus_asm --read_settings_files=off --write_settings_files=off clock -c clock
quartus_tan --read_settings_files=off --write_settings_files=off clock -c clock
quartus_eda --read_settings_files=off --write_settings_files=off clock -c clock