clock.fit.summary

功能更加完善的基于vhdl的数字时钟设计 有秒表

Fitter Status : Successful - Sat Dec 08 19:12:06 2007
Quartus II Version : 5.1 Build 216 03/06/2006 SP 2 SJ Full Version
Revision Name : clock
Top-level Entity Name : clock
Family : ACEX1K
Device : EP1K10TC144-3
Timing Models : Final
Total logic elements : 266 / 576 ( 46 % )
Total pins : 32 / 92 ( 35 % )
Total memory bits : 0 / 12,288 ( 0 % )
Total PLLs : 0