clock.tan.rpt

功能更加完善的基于vhdl的数字时钟设计 有秒表

; Worst-case tpd               ; N/A                                      ; None          ; 17.700 ns                                      ; date                                                                      ; co3[2]                                                                    ; --         ; --       ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; 4.800 ns                                       ; rst                                                                       ; time:U3|dy:U4|c                                                           ; --         ; set      ; 0            ;
; Clock Setup: 'set'           ; N/A                                      ; None          ; 67.57 MHz ( period = 14.800 ns )               ; time:U3|dy:U4|s1[2]                                                       ; time:U3|dy:U4|c                                                           ; set        ; set      ; 0            ;
; Clock Setup: 'date'          ; N/A                                      ; None          ; 77.52 MHz ( period = 12.900 ns )               ; time:U3|dy:U4|s1[2]                                                       ; time:U3|dy:U4|c                                                           ; date       ; date     ; 0            ;
; Clock Setup: 'clk'           ; N/A                                      ; None          ; 77.52 MHz ( period = 12.900 ns )               ; time:U3|dy:U4|s1[2]                                                       ; time:U3|dy:U4|c                                                           ; clk        ; clk      ; 0            ;
; Clock Setup: 'clo'           ; N/A                                      ; None          ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cnt[0]                                                                    ; cnt[0]                                                                    ; clo        ; clo      ; 0            ;
; Clock Hold: 'set'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; time:U3|cnt24:u3|lpm_counter:s1_rtl_2|alt_counter_f10ke:wysi_counter|q[1] ; time:U3|cnt24:u3|lpm_counter:s1_rtl_2|alt_counter_f10ke:wysi_counter|q[2] ; set        ; set      ; 99           ;
; Total number of failed paths ;                                          ;               ;                                                ;                                                                           ;                                                                           ;            ;          ; 99           ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1K10TC144-3      ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; set             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; clo             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; date            ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                                             ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------+------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+