📄 clock_vhd.sdo
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// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
// Device: Altera EP1K10TC144-3 Package TQFP144
//
//
// This SDF file should be used for ModelSim (VHDL) only
//
(DELAYFILE
(SDFVERSION "2.1")
(DESIGN "clock")
(DATE "12/08/2007 19:12:13")
(VENDOR "Altera")
(PROGRAM "Quartus II")
(VERSION "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version")
(DIVIDER .)
(TIMESCALE 1 ps)
(CELL
(CELLTYPE "flex10ke_asynch_lcell")
(INSTANCE \\U3\|u5\|add\~143_I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datac (300:300:300) (300:300:300))
(PORT datad (300:300:300) (300:300:300))
(IOPATH datac combout (1600:1600:1600) (1600:1600:1600))
(IOPATH datad combout (1400:1400:1400) (1400:1400:1400))
)
)
)
(CELL
(CELLTYPE "flex10ke_asynch_lcell")
(INSTANCE \\U3\|u5\|s3\[3\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT dataa (2100:2100:2100) (2100:2100:2100))
(PORT datab (1000:1000:1000) (1000:1000:1000))
(PORT datac (300:300:300) (300:300:300))
(PORT datad (300:300:300) (300:300:300))
(IOPATH dataa regin (1100:1100:1100) (1100:1100:1100))
(IOPATH datab regin (1000:1000:1000) (1000:1000:1000))
(IOPATH datac regin (1000:1000:1000) (1000:1000:1000))
(IOPATH datad regin (800:800:800) (800:800:800))
)
)
)
(CELL
(CELLTYPE "flex10ke_lcell_register")
(INSTANCE \\U3\|u5\|s3\[3\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT aclr (400:400:400) (400:400:400))
(PORT clk (1200:1200:1200) (1200:1200:1200))
(IOPATH (posedge clk) regout (500:500:500) (500:500:500))
(IOPATH (posedge aclr) regout (1200:1200:1200) (1200:1200:1200))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (600:600:600))
(HOLD datain (posedge clk) (1300:1300:1300))
)
)
(CELL
(CELLTYPE "flex10ke_asynch_lcell")
(INSTANCE \\U3\|U4\|process0\~200_I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datab (1200:1200:1200) (1200:1200:1200))
(PORT datac (900:900:900) (900:900:900))
(PORT datad (300:300:300) (300:300:300))
(IOPATH datab combout (1600:1600:1600) (1600:1600:1600))
(IOPATH datac combout (1600:1600:1600) (1600:1600:1600))
(IOPATH datad combout (1400:1400:1400) (1400:1400:1400))
)
)
)
(CELL
(CELLTYPE "flex10ke_asynch_lcell")
(INSTANCE \\U4\|U1\|process0\~24_I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datab (1200:1200:1200) (1200:1200:1200))
(PORT datac (300:300:300) (300:300:300))
(PORT datad (300:300:300) (300:300:300))
(IOPATH datab combout (1600:1600:1600) (1600:1600:1600))
(IOPATH datac combout (1600:1600:1600) (1600:1600:1600))
(IOPATH datad combout (1400:1400:1400) (1400:1400:1400))
)
)
)
(CELL
(CELLTYPE "flex10ke_asynch_lcell")
(INSTANCE \\U2\|u1\|c\~0_I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datac (1100:1100:1100) (1100:1100:1100))
(PORT datad (1300:1300:1300) (1300:1300:1300))
(IOPATH datac combout (1600:1600:1600) (1600:1600:1600))
(IOPATH datad combout (1400:1400:1400) (1400:1400:1400))
)
)
)
(CELL
(CELLTYPE "flex10ke_asynch_lcell")
(INSTANCE \\U4\|U2\|Equal\~49_I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT dataa (300:300:300) (300:300:300))
(PORT datab (300:300:300) (300:300:300))
(PORT datac (300:300:300) (300:300:300))
(PORT datad (300:300:300) (300:300:300))
(IOPATH dataa combout (1700:1700:1700) (1700:1700:1700))
(IOPATH datab combout (1600:1600:1600) (1600:1600:1600))
(IOPATH datac combout (1600:1600:1600) (1600:1600:1600))
(IOPATH datad combout (1400:1400:1400) (1400:1400:1400))
)
)
)
(CELL
(CELLTYPE "flex10ke_asynch_lcell")
(INSTANCE \\U3\|u3\|Equal\~49_I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT dataa (300:300:300) (300:300:300))
(PORT datab (300:300:300) (300:300:300))
(PORT datac (300:300:300) (300:300:300))
(PORT datad (300:300:300) (300:300:300))
(IOPATH dataa combout (1700:1700:1700) (1700:1700:1700))
(IOPATH datab combout (1600:1600:1600) (1600:1600:1600))
(IOPATH datac combout (1600:1600:1600) (1600:1600:1600))
(IOPATH datad combout (1400:1400:1400) (1400:1400:1400))
)
)
)
(CELL
(CELLTYPE "flex10ke_asynch_lcell")
(INSTANCE \\U3\|u5\|Equal\~51_I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT dataa (300:300:300) (300:300:300))
(PORT datab (300:300:300) (300:300:300))
(PORT datac (300:300:300) (300:300:300))
(PORT datad (300:300:300) (300:300:300))
(IOPATH dataa combout (1700:1700:1700) (1700:1700:1700))
(IOPATH datab combout (1600:1600:1600) (1600:1600:1600))
(IOPATH datac combout (1600:1600:1600) (1600:1600:1600))
(IOPATH datad combout (1400:1400:1400) (1400:1400:1400))
)
)
)
(CELL
(CELLTYPE "flex10ke_asynch_lcell")
(INSTANCE \\U3\|u5\|add\~144_I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datac (1000:1000:1000) (1000:1000:1000))
(PORT datad (300:300:300) (300:300:300))
(IOPATH datac combout (1600:1600:1600) (1600:1600:1600))
(IOPATH datad combout (1400:1400:1400) (1400:1400:1400))
)
)
)
(CELL
(CELLTYPE "flex10ke_asynch_lcell")
(INSTANCE \\U3\|U4\|c\~338_I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datad (200:200:200) (200:200:200))
(IOPATH datad combout (1400:1400:1400) (1400:1400:1400))
)
)
)
(CELL
(CELLTYPE "flex10ke_asynch_io")
(INSTANCE \\set\~I\\.inst1)
(DELAY
(ABSOLUTE
(IOPATH padio dataout (2000:2000:2000) (2000:2000:2000))
)
)
)
(CELL
(CELLTYPE "flex10ke_asynch_lcell")
(INSTANCE \\U1\|c\[0\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datad (300:300:300) (300:300:300))
(IOPATH datad regin (800:800:800) (800:800:800))
)
)
)
(CELL
(CELLTYPE "flex10ke_lcell_register")
(INSTANCE \\U1\|c\[0\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT clk (400:400:400) (400:400:400))
(IOPATH (posedge clk) regout (500:500:500) (500:500:500))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (600:600:600))
(HOLD datain (posedge clk) (1300:1300:1300))
)
)
(CELL
(CELLTYPE "flex10ke_asynch_lcell")
(INSTANCE \\U1\|c\[1\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datac (1100:1100:1100) (1100:1100:1100))
(PORT datad (300:300:300) (300:300:300))
(IOPATH datac regin (1000:1000:1000) (1000:1000:1000))
(IOPATH datad regin (800:800:800) (800:800:800))
)
)
)
(CELL
(CELLTYPE "flex10ke_lcell_register")
(INSTANCE \\U1\|c\[1\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT clk (400:400:400) (400:400:400))
(IOPATH (posedge clk) regout (500:500:500) (500:500:500))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (600:600:600))
(HOLD datain (posedge clk) (1300:1300:1300))
)
)
(CELL
(CELLTYPE "flex10ke_asynch_lcell")
(INSTANCE \\U1\|c\[2\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datab (1000:1000:1000) (1000:1000:1000))
(PORT datac (1100:1100:1100) (1100:1100:1100))
(PORT datad (300:300:300) (300:300:300))
(IOPATH datab regin (1000:1000:1000) (1000:1000:1000))
(IOPATH datac regin (1000:1000:1000) (1000:1000:1000))
(IOPATH datad regin (800:800:800) (800:800:800))
)
)
)
(CELL
(CELLTYPE "flex10ke_lcell_register")
(INSTANCE \\U1\|c\[2\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT clk (400:400:400) (400:400:400))
(IOPATH (posedge clk) regout (500:500:500) (500:500:500))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (600:600:600))
(HOLD datain (posedge clk) (1300:1300:1300))
)
)
(CELL
(CELLTYPE "flex10ke_asynch_io")
(INSTANCE \\clo\~I\\.inst1)
(DELAY
(ABSOLUTE
(IOPATH padio dataout (2000:2000:2000) (2000:2000:2000))
)
)
)
(CELL
(CELLTYPE "flex10ke_asynch_lcell")
(INSTANCE \\cecl\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT dataa (1200:1200:1200) (1200:1200:1200))
(PORT datab (1100:1100:1100) (1100:1100:1100))
(PORT datac (300:300:300) (300:300:300))
(PORT datad (0:0:0) (0:0:0))
(IOPATH dataa combout (1700:1700:1700) (1700:1700:1700))
(IOPATH datab combout (1600:1600:1600) (1600:1600:1600))
(IOPATH datac combout (1600:1600:1600) (1600:1600:1600))
(IOPATH datad combout (1400:1400:1400) (1400:1400:1400))
)
)
)
(CELL
(CELLTYPE "flex10ke_asynch_lcell")
(INSTANCE \\cnt\[0\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datad (300:300:300) (300:300:300))
(IOPATH datad regin (800:800:800) (800:800:800))
)
)
)
(CELL
(CELLTYPE "flex10ke_lcell_register")
(INSTANCE \\cnt\[0\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT clk (300:300:300) (300:300:300))
(IOPATH (posedge clk) regout (500:500:500) (500:500:500))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (600:600:600))
(HOLD datain (posedge clk) (1300:1300:1300))
)
)
(CELL
(CELLTYPE "flex10ke_asynch_lcell")
(INSTANCE \\U1\|sday\~88_I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datab (1100:1100:1100) (1100:1100:1100))
(PORT datac (300:300:300) (300:300:300))
(PORT datad (1000:1000:1000) (1000:1000:1000))
(IOPATH datab combout (1600:1600:1600) (1600:1600:1600))
(IOPATH datac combout (1600:1600:1600) (1600:1600:1600))
(IOPATH datad combout (1400:1400:1400) (1400:1400:1400))
)
)
)
(CELL
(CELLTYPE "flex10ke_asynch_io")
(INSTANCE \\date\~I\\.inst1)
(DELAY
(ABSOLUTE
(IOPATH padio dataout (2000:2000:2000) (2000:2000:2000))
)
)
)
(CELL
(CELLTYPE "flex10ke_asynch_io")
(INSTANCE \\clk\~I\\.inst1)
(DELAY
(ABSOLUTE
(IOPATH padio dataout (2000:2000:2000) (2000:2000:2000))
)
)
)
(CELL
(CELLTYPE "flex10ke_asynch_lcell")
(INSTANCE \\ced\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datab (1400:1400:1400) (1400:1400:1400))
(PORT datac (1100:1100:1100) (1100:1100:1100))
(PORT datad (0:0:0) (0:0:0))
(IOPATH datab regin (1000:1000:1000) (1000:1000:1000))
(IOPATH datac regin (1000:1000:1000) (1000:1000:1000))
(IOPATH datad regin (800:800:800) (800:800:800))
)
)
)
(CELL
(CELLTYPE "flex10ke_lcell_register")
(INSTANCE \\ced\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT clk (400:400:400) (400:400:400))
(IOPATH (posedge clk) regout (500:500:500) (500:500:500))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (600:600:600))
(HOLD datain (posedge clk) (1300:1300:1300))
)
)
(CELL
(CELLTYPE "flex10ke_asynch_lcell")
(INSTANCE \\U2\|u1\|s1\[0\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT dataa (1400:1400:1400) (1400:1400:1400))
(PORT datad (300:300:300) (300:300:300))
(IOPATH datad regin (800:800:800) (800:800:800))
)
)
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