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📄 clock.vho

📁 功能更加完善的基于vhdl的数字时钟设计 有秒表
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PORT MAP (
	dataa => \U3|u2|s1[0]\,
	datab => \U3|u2|s1[1]\,
	datac => \U3|u2|s1[3]\,
	datad => \U3|u2|s1[2]\,
	clk => \U3|clkc1\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|u2|s1[1]\);

\U3|u2|Equal~40_I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u2|Equal~40\ = !\U3|u2|s1[2]\ & !\U3|u2|s1[1]\ & \U3|u2|s1[3]\ & \U3|u2|s1[0]\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "1000",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U3|u2|s1[2]\,
	datab => \U3|u2|s1[1]\,
	datac => \U3|u2|s1[3]\,
	datad => \U3|u2|s1[0]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|u2|Equal~40\);

\U3|u2|add_rtl_7|adder|result_node|cs_buffer[0]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u2|add_rtl_7|adder|result_node|cs_buffer[0]\ = \U3|u2|Equal~40\ $ \U3|u2|s2[0]\
-- \U3|u2|add_rtl_7|adder|result_node|cout[0]\ = CARRY(\U3|u2|Equal~40\ & \U3|u2|s2[0]\)

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "6688",
	operation_mode => "arithmetic",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U3|u2|Equal~40\,
	datab => \U3|u2|s2[0]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|u2|add_rtl_7|adder|result_node|cs_buffer[0]\,
	cout => \U3|u2|add_rtl_7|adder|result_node|cout[0]\);

\U3|u2|s2[0]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u2|s2[0]\ = DFFEA(\U3|u2|add_rtl_7|adder|result_node|cs_buffer[0]\, \U3|clkc1\, , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "FF00",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datad => \U3|u2|add_rtl_7|adder|result_node|cs_buffer[0]\,
	clk => \U3|clkc1\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|u2|s2[0]\);

\U3|u2|add_rtl_7|adder|result_node|cs_buffer[1]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u2|add_rtl_7|adder|result_node|cs_buffer[1]\ = \U3|u2|s2[1]\ $ \U3|u2|add_rtl_7|adder|result_node|cout[0]\
-- \U3|u2|add_rtl_7|adder|result_node|cout[1]\ = CARRY(\U3|u2|s2[1]\ & \U3|u2|add_rtl_7|adder|result_node|cout[0]\)

-- pragma translate_off
GENERIC MAP (
	cin_used => "true",
	clock_enable_mode => "false",
	lut_mask => "3CC0",
	operation_mode => "arithmetic",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datab => \U3|u2|s2[1]\,
	cin => \U3|u2|add_rtl_7|adder|result_node|cout[0]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|u2|add_rtl_7|adder|result_node|cs_buffer[1]\,
	cout => \U3|u2|add_rtl_7|adder|result_node|cout[1]\);

\U3|u2|s2[1]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u2|s2[1]\ = DFFEA(\U3|u2|add_rtl_7|adder|result_node|cs_buffer[1]\ & (!\U3|u2|s2[0]\ # !\U3|u2|Equal~40\ # !\U3|u2|process0~24\), \U3|clkc1\, , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "7F00",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U3|u2|process0~24\,
	datab => \U3|u2|Equal~40\,
	datac => \U3|u2|s2[0]\,
	datad => \U3|u2|add_rtl_7|adder|result_node|cs_buffer[1]\,
	clk => \U3|clkc1\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|u2|s2[1]\);

\U3|u2|add_rtl_7|adder|result_node|cs_buffer[2]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u2|add_rtl_7|adder|result_node|cs_buffer[2]\ = \U3|u2|s2[2]\ $ \U3|u2|add_rtl_7|adder|result_node|cout[1]\
-- \U3|u2|add_rtl_7|adder|result_node|cout[2]\ = CARRY(\U3|u2|s2[2]\ & \U3|u2|add_rtl_7|adder|result_node|cout[1]\)

-- pragma translate_off
GENERIC MAP (
	cin_used => "true",
	clock_enable_mode => "false",
	lut_mask => "3CC0",
	operation_mode => "arithmetic",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datab => \U3|u2|s2[2]\,
	cin => \U3|u2|add_rtl_7|adder|result_node|cout[1]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|u2|add_rtl_7|adder|result_node|cs_buffer[2]\,
	cout => \U3|u2|add_rtl_7|adder|result_node|cout[2]\);

\U3|u2|s2[2]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u2|s2[2]\ = DFFEA(\U3|u2|add_rtl_7|adder|result_node|cs_buffer[2]\ & (!\U3|u2|s2[0]\ # !\U3|u2|Equal~40\ # !\U3|u2|process0~24\), \U3|clkc1\, , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "7F00",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U3|u2|process0~24\,
	datab => \U3|u2|Equal~40\,
	datac => \U3|u2|s2[0]\,
	datad => \U3|u2|add_rtl_7|adder|result_node|cs_buffer[2]\,
	clk => \U3|clkc1\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|u2|s2[2]\);

\U3|u2|add_rtl_7|adder|unreg_res_node[3]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u2|add_rtl_7|adder|unreg_res_node[3]\ = \U3|u2|add_rtl_7|adder|result_node|cout[2]\ $ \U3|u2|s2[3]\

-- pragma translate_off
GENERIC MAP (
	cin_used => "true",
	clock_enable_mode => "false",
	lut_mask => "0FF0",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datad => \U3|u2|s2[3]\,
	cin => \U3|u2|add_rtl_7|adder|result_node|cout[2]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|u2|add_rtl_7|adder|unreg_res_node[3]\);

\U3|u2|s2[3]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u2|s2[3]\ = DFFEA(\U3|u2|add_rtl_7|adder|unreg_res_node[3]\, \U3|clkc1\, , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "FF00",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datad => \U3|u2|add_rtl_7|adder|unreg_res_node[3]\,
	clk => \U3|clkc1\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|u2|s2[3]\);

\U3|u2|process0~24_I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u2|process0~24\ = !\U3|u2|s2[3]\ & !\U3|u2|s2[1]\ & \U3|u2|s2[2]\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "0300",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datab => \U3|u2|s2[3]\,
	datac => \U3|u2|s2[1]\,
	datad => \U3|u2|s2[2]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|u2|process0~24\);

\U3|u2|c~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u2|c\ = DFFEA(\U3|u2|process0~24\ & \U3|u2|Equal~40\ & \U3|u2|s2[0]\, \U3|clkc1\, , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "C000",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datab => \U3|u2|process0~24\,
	datac => \U3|u2|Equal~40\,
	datad => \U3|u2|s2[0]\,
	clk => \U3|clkc1\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|u2|c\);

\U3|clkc2~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|clkc2\ = DFFEA(\U3|u2|c\ & (\U1|c[0]\ # !\date~dataout\ # !\process2~80\), GLOBAL(\clk~dataout\), , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "F700",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \process2~80\,
	datab => \date~dataout\,
	datac => \U1|c[0]\,
	datad => \U3|u2|c\,
	clk => \clk~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|clkc2\);

\U3|clkc3~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|clkc3\ = \U3|clkc2\ # \process2~80\ & \date~dataout\ & \U1|c[0]\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "FF80",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \process2~80\,
	datab => \date~dataout\,
	datac => \U1|c[0]\,
	datad => \U3|clkc2\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|clkc3\);

\U3|u3|s1_rtl_2|wysi_counter|counter_cell[0]\ : flex10ke_lcell
-- Equation(s):
-- \U3|u3|s1_rtl_2|wysi_counter|q[0]\ = DFFEA((!\U3|u3|s1_rtl_2|wysi_counter|q[0]\) & \U3|u3|s1~27\, \U3|clkc3\, , , , , )
-- \U3|u3|s1_rtl_2|wysi_counter|counter_cell[0]~COUT\ = CARRY(\U3|u3|s1_rtl_2|wysi_counter|q[0]\)

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "33AA",
	operation_mode => "clrb_cntr",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datab => \U3|u3|s1~27\,
	clk => \U3|clkc3\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|u3|s1_rtl_2|wysi_counter|q[0]\,
	cout => \U3|u3|s1_rtl_2|wysi_counter|counter_cell[0]~COUT\);

\U3|u3|s1_rtl_2|wysi_counter|counter_cell[1]\ : flex10ke_lcell
-- Equation(s):
-- \U3|u3|s1_rtl_2|wysi_counter|q[1]\ = DFFEA((\U3|u3|s1_rtl_2|wysi_counter|q[1]\ $ \U3|u3|s1_rtl_2|wysi_counter|counter_cell[0]~COUT\) & \U3|u3|s1~27\, \U3|clkc3\, , , , , )
-- \U3|u3|s1_rtl_2|wysi_counter|counter_cell[1]~COUT\ = CARRY(\U3|u3|s1_rtl_2|wysi_counter|q[1]\ & (\U3|u3|s1_rtl_2|wysi_counter|counter_cell[0]~COUT\))

-- pragma translate_off
GENERIC MAP (
	cin_used => "true",
	clock_enable_mode => "false",
	lut_mask => "3CA0",
	operation_mode => "clrb_cntr",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datab => \U3|u3|s1~27\,
	clk => \U3|clkc3\,
	cin => \U3|u3|s1_rtl_2|wysi_counter|counter_cell[0]~COUT\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|u3|s1_rtl_2|wysi_counter|q[1]\,
	cout => \U3|u3|s1_rtl_2|wysi_counter|counter_cell[1]~COUT\);

\U3|u3|s1_rtl_2|wysi_counter|counter_cell[2]\ : flex10ke_lcell
-- Equation(s):
-- \U3|u3|s1_rtl_2|wysi_counter|q[2]\ = DFFEA((\U3|u3|s1_rtl_2|wysi_counter|q[2]\ $ \U3|u3|s1_rtl_2|wysi_counter|counter_cell[1]~COUT\) & \U3|u3|s1~27\, \U3|clkc3\, , , , , )
-- \U3|u3|s1_rtl_2|wysi_counter|counter_cell[2]~COUT\ = CARRY(\U3|u3|s1_rtl_2|wysi_counter|q[2]\ & (\U3|u3|s1_rtl_2|wysi_counter|counter_cell[1]~COUT\))

-- pragma translate_off
GENERIC MAP (
	cin_used => "true",
	clock_enable_mode => "false",
	lut_mask => "3CA0",
	operation_mode => "clrb_cntr",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datab => \U3|u3|s1~27\,
	clk => \U3|clkc3\,
	cin => \U3|u3|s1_rtl_2|wysi_counter|counter_cell[1]~COUT\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|u3|s1_rtl_2|wysi_counter|q[2]\,
	cout => \U3|u3|s1_rtl_2|wysi_counter|counter_cell[2]~COUT\);

\U3|u3|s1_rtl_2|wysi_counter|counter_cell[3]\ : flex10ke_lcell
-- Equation(s):
-- \U3|u3|s1_rtl_2|wysi_counter|q[3]\ = DFFEA((\U3|u3|s1_rtl_2|wysi_counter|q[3]\ $ \U3|u3|s1_rtl_2|wysi_counter|counter_cell[2]~COUT\) & \U3|u3|s1~27\, \U3|clkc3\, , , , , )

-- pragma translate_off
GENERIC MAP (
	cin_used => "true",
	clock_enable_mode => "false",
	lut_mask => "3C3C",
	operation_mode => "clrb_cntr",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datab => \U3|u3|s1~27\,
	clk => \U3|clkc3\,
	cin => \U3|u3|s1_rtl_2|wysi_counter|counter_cell[2]~COUT\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|u3|s1_rtl_2|wysi_counter|q[3]\);

\U3|u3|Equal~48_I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u3|Equal~48\ = !\U3|u3|s1_rtl_2|wysi_counter|q[2]\ & \U3|u3|s1_rtl_2|wysi_counter|q[0]\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "0F00",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datac => \U3|u3|s1_rtl_2|wysi_counter|q[2]\,
	datad => \U3|u3|s1_rtl_2|wysi_counter|q[0]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|u3|Equal~48\);

\U3|u3|s1~27_I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u3|s1~27\ = \U3|u3|s1_rtl_2|wysi_counter|q[1]\ & (\U3|u3|s1_rtl_2|wysi_counter|q[3]\ # !\U3|u3|process0~48\) # !\U3|u3|s1_rtl_2|wysi_counter|q[1]\ & !\U3|u3|s1_rtl_2|wysi_counter|q[3]\ # !\U3|u3|Equal~48\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "9BFF",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U3|u3|s1_rtl_2|wysi_counter|q[1]\,
	datab => \U3|u3|s1_rtl_2|wysi_counter|q[3]\,
	datac => \U3|u3|process0~48\,
	datad => \U3|u3|Equal~48\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|u3|s1~27\);

\U3|u3|process0~0_I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u3|process0~0\ = !\U3|u3|s1_rtl_2|wysi_counter|q[3]\ & \U3|u3|process0~48\ & \U3|u3|s1_rtl_2|wysi_counter|q[1]\ & \U3|u3|Equal~48\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "4000",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U3|u3|s1_rtl_2|wysi_counter|q[3]\,
	datab => \U3|u3|process0~48\,
	datac => \U3|u3|s1_rtl_2|wysi_counter|q[1]\,
	datad => \U3|u3|Equal~48\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|u3|process0~0\);

\U3|u3|add_rtl_10|adder|result_node|cs_buffer[0]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u3|add_rtl_10|adder|result_node|cs_buffer[0]\ = \U3|u3|Equa
12345

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