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📄 clock.vho

📁 功能更加完善的基于vhdl的数字时钟设计 有秒表
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	dataa => \U3|u5|s3[3]\,
	datab => \U3|u5|s3[2]\,
	datac => \U3|u5|s3[1]\,
	datad => \U3|u5|s3[0]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|U4|Equal~238\);

\U3|U4|process0~204_I\ : flex10ke_lcell
-- Equation(s):
-- \U3|U4|process0~204\ = \U3|u5|s3[3]\ & !\U3|u5|s3[2]\ & !\U3|u5|s3[1]\ & !\U3|u5|s3[0]\ # !\U3|u5|s3[3]\ & \U3|u5|s3[2]\ & (\U3|u5|s3[0]\)

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "4402",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U3|u5|s3[3]\,
	datab => \U3|u5|s3[2]\,
	datac => \U3|u5|s3[1]\,
	datad => \U3|u5|s3[0]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|U4|process0~204\);

\U3|U4|Equal~237_I\ : flex10ke_lcell
-- Equation(s):
-- \U3|U4|Equal~237\ = !\U3|u5|s3[3]\ & !\U3|u5|s3[2]\ & \U3|u5|s3[1]\ & \U3|u5|s3[0]\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "1000",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U3|u5|s3[3]\,
	datab => \U3|u5|s3[2]\,
	datac => \U3|u5|s3[1]\,
	datad => \U3|u5|s3[0]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|U4|Equal~237\);

\U3|U4|s1~816_I\ : flex10ke_lcell
-- Equation(s):
-- \U3|U4|s1~816\ = !\U3|U4|Equal~238\ & !\U3|U4|process0~204\ & (\U3|U4|process0~11\ # !\U3|U4|Equal~237\)

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "1101",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U3|U4|Equal~238\,
	datab => \U3|U4|process0~204\,
	datac => \U3|U4|Equal~237\,
	datad => \U3|U4|process0~11\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|U4|s1~816\);

\U3|U4|s1~819_I\ : flex10ke_lcell
-- Equation(s):
-- \U3|U4|s1~819\ = \U3|U4|s1[2]\ & (\U3|U4|s1[3]\ $ (\U3|U4|s1[1]\ & !\U3|U4|s1[0]\)) # !\U3|U4|s1[2]\ & \U3|U4|s1[3]\ & (\U3|U4|s1[1]\ # \U3|U4|s1[0]\)

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "F608",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U3|U4|s1[2]\,
	datab => \U3|U4|s1[1]\,
	datac => \U3|U4|s1[0]\,
	datad => \U3|U4|s1[3]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|U4|s1~819\);

\process2~80_I\ : flex10ke_lcell
-- Equation(s):
-- \process2~80\ = !\U1|c[2]\ & \U1|c[1]\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "0F00",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datac => \U1|c[2]\,
	datad => \U1|c[1]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \process2~80\);

\U3|u1|Equal~40_I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u1|Equal~40\ = !\U3|u1|s1[2]\ & !\U3|u1|s1[1]\ & \U3|u1|s1[3]\ & \U3|u1|s1[0]\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "1000",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U3|u1|s1[2]\,
	datab => \U3|u1|s1[1]\,
	datac => \U3|u1|s1[3]\,
	datad => \U3|u1|s1[0]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|u1|Equal~40\);

\U3|u1|add_rtl_4|adder|result_node|cs_buffer[0]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u1|add_rtl_4|adder|result_node|cs_buffer[0]\ = \U3|u1|Equal~40\ $ \U3|u1|s2[0]\
-- \U3|u1|add_rtl_4|adder|result_node|cout[0]\ = CARRY(\U3|u1|Equal~40\ & \U3|u1|s2[0]\)

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "6688",
	operation_mode => "arithmetic",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U3|u1|Equal~40\,
	datab => \U3|u1|s2[0]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|u1|add_rtl_4|adder|result_node|cs_buffer[0]\,
	cout => \U3|u1|add_rtl_4|adder|result_node|cout[0]\);

\U3|u1|s2[0]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u1|s2[0]\ = DFFEA(\U3|u1|add_rtl_4|adder|result_node|cs_buffer[0]\, GLOBAL(\clk~dataout\), , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "FF00",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datad => \U3|u1|add_rtl_4|adder|result_node|cs_buffer[0]\,
	clk => \clk~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|u1|s2[0]\);

\U3|u1|add_rtl_4|adder|result_node|cs_buffer[1]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u1|add_rtl_4|adder|result_node|cs_buffer[1]\ = \U3|u1|s2[1]\ $ \U3|u1|add_rtl_4|adder|result_node|cout[0]\
-- \U3|u1|add_rtl_4|adder|result_node|cout[1]\ = CARRY(\U3|u1|s2[1]\ & \U3|u1|add_rtl_4|adder|result_node|cout[0]\)

-- pragma translate_off
GENERIC MAP (
	cin_used => "true",
	clock_enable_mode => "false",
	lut_mask => "3CC0",
	operation_mode => "arithmetic",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datab => \U3|u1|s2[1]\,
	cin => \U3|u1|add_rtl_4|adder|result_node|cout[0]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|u1|add_rtl_4|adder|result_node|cs_buffer[1]\,
	cout => \U3|u1|add_rtl_4|adder|result_node|cout[1]\);

\U3|u1|s2[1]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u1|s2[1]\ = DFFEA(\U3|u1|add_rtl_4|adder|result_node|cs_buffer[1]\ & (!\U3|u1|s2[0]\ # !\U3|u1|Equal~40\ # !\U3|u1|process0~27\), GLOBAL(\clk~dataout\), , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "7F00",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U3|u1|process0~27\,
	datab => \U3|u1|Equal~40\,
	datac => \U3|u1|s2[0]\,
	datad => \U3|u1|add_rtl_4|adder|result_node|cs_buffer[1]\,
	clk => \clk~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|u1|s2[1]\);

\U3|u1|add_rtl_4|adder|result_node|cs_buffer[2]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u1|add_rtl_4|adder|result_node|cs_buffer[2]\ = \U3|u1|s2[2]\ $ \U3|u1|add_rtl_4|adder|result_node|cout[1]\
-- \U3|u1|add_rtl_4|adder|result_node|cout[2]\ = CARRY(\U3|u1|s2[2]\ & \U3|u1|add_rtl_4|adder|result_node|cout[1]\)

-- pragma translate_off
GENERIC MAP (
	cin_used => "true",
	clock_enable_mode => "false",
	lut_mask => "3CC0",
	operation_mode => "arithmetic",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datab => \U3|u1|s2[2]\,
	cin => \U3|u1|add_rtl_4|adder|result_node|cout[1]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|u1|add_rtl_4|adder|result_node|cs_buffer[2]\,
	cout => \U3|u1|add_rtl_4|adder|result_node|cout[2]\);

\U3|u1|s2[2]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u1|s2[2]\ = DFFEA(\U3|u1|add_rtl_4|adder|result_node|cs_buffer[2]\ & (!\U3|u1|s2[0]\ # !\U3|u1|Equal~40\ # !\U3|u1|process0~27\), GLOBAL(\clk~dataout\), , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "7F00",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U3|u1|process0~27\,
	datab => \U3|u1|Equal~40\,
	datac => \U3|u1|s2[0]\,
	datad => \U3|u1|add_rtl_4|adder|result_node|cs_buffer[2]\,
	clk => \clk~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|u1|s2[2]\);

\U3|u1|add_rtl_4|adder|unreg_res_node[3]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u1|add_rtl_4|adder|unreg_res_node[3]\ = \U3|u1|add_rtl_4|adder|result_node|cout[2]\ $ \U3|u1|s2[3]\

-- pragma translate_off
GENERIC MAP (
	cin_used => "true",
	clock_enable_mode => "false",
	lut_mask => "0FF0",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datad => \U3|u1|s2[3]\,
	cin => \U3|u1|add_rtl_4|adder|result_node|cout[2]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|u1|add_rtl_4|adder|unreg_res_node[3]\);

\U3|u1|s2[3]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u1|s2[3]\ = DFFEA(\U3|u1|add_rtl_4|adder|unreg_res_node[3]\, GLOBAL(\clk~dataout\), , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "FF00",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datad => \U3|u1|add_rtl_4|adder|unreg_res_node[3]\,
	clk => \clk~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|u1|s2[3]\);

\U3|u1|process0~27_I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u1|process0~27\ = !\U3|u1|s2[3]\ & !\U3|u1|s2[1]\ & \U3|u1|s2[2]\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "0300",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datab => \U3|u1|s2[3]\,
	datac => \U3|u1|s2[1]\,
	datad => \U3|u1|s2[2]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|u1|process0~27\);

\U3|u1|c~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u1|c\ = DFFEA(\U3|u1|process0~27\ & \U3|u1|Equal~40\ & \U3|u1|s2[0]\, GLOBAL(\clk~dataout\), , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "C000",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datab => \U3|u1|process0~27\,
	datac => \U3|u1|Equal~40\,
	datad => \U3|u1|s2[0]\,
	clk => \clk~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|u1|c\);

\U3|clkc1~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|clkc1\ = \U3|u1|c\ # !\U1|c[0]\ & \process2~80\ & \date~dataout\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "FF40",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U1|c[0]\,
	datab => \process2~80\,
	datac => \date~dataout\,
	datad => \U3|u1|c\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|clkc1\);

\U3|u2|s1[0]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u2|s1[0]\ = DFFEA(!\U3|u2|s1[0]\, \U3|clkc1\, , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "00FF",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datad => \U3|u2|s1[0]\,
	clk => \U3|clkc1\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|u2|s1[0]\);

\U3|u2|s1[2]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u2|s1[2]\ = DFFEA(\U3|u2|s1[2]\ $ (\U3|u2|s1[1]\ & \U3|u2|s1[0]\), \U3|clkc1\, , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "3FC0",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datab => \U3|u2|s1[1]\,
	datac => \U3|u2|s1[0]\,
	datad => \U3|u2|s1[2]\,
	clk => \U3|clkc1\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|u2|s1[2]\);

\U3|u2|s1[3]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u2|s1[3]\ = DFFEA(\U3|u2|s1[0]\ & (\U3|u2|s1[2]\ & (\U3|u2|s1[1]\ $ \U3|u2|s1[3]\) # !\U3|u2|s1[2]\ & \U3|u2|s1[1]\ & \U3|u2|s1[3]\) # !\U3|u2|s1[0]\ & (\U3|u2|s1[3]\), \U3|clkc1\, , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "7D80",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U3|u2|s1[0]\,
	datab => \U3|u2|s1[2]\,
	datac => \U3|u2|s1[1]\,
	datad => \U3|u2|s1[3]\,
	clk => \U3|clkc1\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|u2|s1[3]\);

\U3|u2|s1[1]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u2|s1[1]\ = DFFEA(\U3|u2|s1[0]\ & !\U3|u2|s1[1]\ & (\U3|u2|s1[2]\ # !\U3|u2|s1[3]\) # !\U3|u2|s1[0]\ & \U3|u2|s1[1]\, \U3|clkc1\, , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "6646",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
12345

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