⭐ 欢迎来到虫虫下载站！ | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站
📤 上传资源

📄 clock.vho

📁 功能更加完善的基于vhdl的数字时钟设计 有秒表
💻 VHO
📖 第 1 页 / 共 5 页
字号:
🔍
12345 
	datab => \U1|c[2]\,
	datac => \U1|c[1]\,
	datad => \U1|c[0]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \co1~1387\);

\process2~4_I\ : flex10ke_lcell
-- Equation(s):
-- \process2~4\ = \date~dataout\ # !\U1|c[1]\ & \U1|c[2]\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "FF30",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datab => \U1|c[1]\,
	datac => \U1|c[2]\,
	datad => \date~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \process2~4\);

\co1~1386_I\ : flex10ke_lcell
-- Equation(s):
-- \co1~1386\ = \U1|c[1]\ & \U1|c[2]\ & \date~dataout\ # !\U1|c[1]\ & (\U1|c[2]\ # \date~dataout\)

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "F330",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datab => \U1|c[1]\,
	datac => \U1|c[2]\,
	datad => \date~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \co1~1386\);

\U3|u1|s1[0]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u1|s1[0]\ = DFFEA(!\U3|u1|s1[0]\, GLOBAL(\clk~dataout\), , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "00FF",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datad => \U3|u1|s1[0]\,
	clk => \clk~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|u1|s1[0]\);

\co1~1401_I\ : flex10ke_lcell
-- Equation(s):
-- \co1~1401\ = \U3|U4|s1[0]\ & !\process2~4\ & (\U3|u1|s1[0]\) # !\U3|U4|s1[0]\ & (\co1~1386\ # !\process2~4\ & \U3|u1|s1[0]\)

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "7350",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U3|U4|s1[0]\,
	datab => \process2~4\,
	datac => \co1~1386\,
	datad => \U3|u1|s1[0]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \co1~1401\);

\co1~1385_I\ : flex10ke_lcell
-- Equation(s):
-- \co1~1385\ = \U1|c[1]\ & (\U1|c[2]\) # !\U1|c[1]\ & \clo~dataout\ & (\U1|c[2]\ # !\U1|c[0]\)

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "FC10",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U1|c[0]\,
	datab => \U1|c[1]\,
	datac => \clo~dataout\,
	datad => \U1|c[2]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \co1~1385\);

\scmin~9_I\ : flex10ke_lcell
-- Equation(s):
-- \scmin~9\ = !\U1|c[0]\ & \U1|c[2]\ & \date~dataout\ & \U1|c[1]\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "4000",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U1|c[0]\,
	datab => \U1|c[2]\,
	datac => \date~dataout\,
	datad => \U1|c[1]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \scmin~9\);

\U4|U1|s1[0]~I\ : flex10ke_lcell
-- Equation(s):
-- \U4|U1|s1[0]\ = DFFEA(!\U4|U1|s1[0]\, \scmin~9\, , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "00FF",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datad => \U4|U1|s1[0]\,
	clk => \scmin~9\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U4|U1|s1[0]\);

\co1~1400_I\ : flex10ke_lcell
-- Equation(s):
-- \co1~1424\ = \process2~80\ & !\U3|u1|s1[0]\ & (!\U4|U1|s1[0]\ # !\co1~1385\) # !\process2~80\ & (!\U4|U1|s1[0]\ # !\co1~1385\)

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "0777",
	operation_mode => "normal",
	output_mode => "none",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \process2~80\,
	datab => \U3|u1|s1[0]\,
	datac => \co1~1385\,
	datad => \U4|U1|s1[0]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \co1~1400\,
	cascout => \co1~1424\);

\co1~1412_I\ : flex10ke_lcell
-- Equation(s):
-- \co1~1412\ = (\U2|u1|s1[0]\ & !\U1|sday~88\ & (!\co1~1401\ # !\co1~1387\) # !\U2|u1|s1[0]\ & (!\co1~1401\ # !\co1~1387\)) & CASCADE(\co1~1424\)

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "0777",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U2|u1|s1[0]\,
	datab => \U1|sday~88\,
	datac => \co1~1387\,
	datad => \co1~1401\,
	cascin => \co1~1424\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \co1~1412\);

\U2|u1|s1[2]~I\ : flex10ke_lcell
-- Equation(s):
-- \U2|u1|s1[2]\ = DFFEA(\U2|u1|s1[2]\ $ (\U2|u1|s1[1]\ & \U2|u1|s1[0]\), GLOBAL(\clk~dataout\), !GLOBAL(ced), , \cnt[0]\, , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "true",
	lut_mask => "3FC0",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \cnt[0]\,
	datab => \U2|u1|s1[1]\,
	datac => \U2|u1|s1[0]\,
	datad => \U2|u1|s1[2]\,
	aclr => ced,
	clk => \clk~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U2|u1|s1[2]\);

\U2|u1|s1~74_I\ : flex10ke_lcell
-- Equation(s):
-- \U2|u1|s1~74\ = \U2|u1|s1[0]\ & (\U2|u1|s1[2]\ & (\U2|u1|s1[1]\ $ \U2|u1|s1[3]\) # !\U2|u1|s1[2]\ & \U2|u1|s1[1]\ & \U2|u1|s1[3]\) # !\U2|u1|s1[0]\ & (\U2|u1|s1[3]\)

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "7D80",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U2|u1|s1[0]\,
	datab => \U2|u1|s1[2]\,
	datac => \U2|u1|s1[1]\,
	datad => \U2|u1|s1[3]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U2|u1|s1~74\);

\U2|u1|s1[3]~I\ : flex10ke_lcell
-- Equation(s):
-- \U2|u1|s1[3]\ = DFFEA(\U2|u1|s1~74\, GLOBAL(\clk~dataout\), !GLOBAL(ced), , \cnt[0]\, , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "true",
	lut_mask => "FF00",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \cnt[0]\,
	datad => \U2|u1|s1~74\,
	aclr => ced,
	clk => \clk~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U2|u1|s1[3]\);

\U2|u1|Equal~40_I\ : flex10ke_lcell
-- Equation(s):
-- \U2|u1|Equal~40\ = !\U2|u1|s1[2]\ & !\U2|u1|s1[1]\ & \U2|u1|s1[3]\ & \U2|u1|s1[0]\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "1000",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U2|u1|s1[2]\,
	datab => \U2|u1|s1[1]\,
	datac => \U2|u1|s1[3]\,
	datad => \U2|u1|s1[0]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U2|u1|Equal~40\);

\U2|u1|s1[1]~I\ : flex10ke_lcell
-- Equation(s):
-- \U2|u1|s1[1]\ = DFFEA(!\U2|u1|Equal~40\ & (\U2|u1|s1[1]\ $ \U2|u1|s1[0]\), GLOBAL(\clk~dataout\), !GLOBAL(ced), , \cnt[0]\, , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "true",
	lut_mask => "0330",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \cnt[0]\,
	datab => \U2|u1|Equal~40\,
	datac => \U2|u1|s1[1]\,
	datad => \U2|u1|s1[0]\,
	aclr => ced,
	clk => \clk~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U2|u1|s1[1]\);

\U3|u1|s1[2]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u1|s1[2]\ = DFFEA(\U3|u1|s1[2]\ $ (\U3|u1|s1[1]\ & \U3|u1|s1[0]\), GLOBAL(\clk~dataout\), , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "3FC0",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datab => \U3|u1|s1[1]\,
	datac => \U3|u1|s1[0]\,
	datad => \U3|u1|s1[2]\,
	clk => \clk~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|u1|s1[2]\);

\U3|u1|s1[3]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u1|s1[3]\ = DFFEA(\U3|u1|s1[0]\ & (\U3|u1|s1[2]\ & (\U3|u1|s1[1]\ $ \U3|u1|s1[3]\) # !\U3|u1|s1[2]\ & \U3|u1|s1[1]\ & \U3|u1|s1[3]\) # !\U3|u1|s1[0]\ & (\U3|u1|s1[3]\), GLOBAL(\clk~dataout\), , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "7D80",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U3|u1|s1[0]\,
	datab => \U3|u1|s1[2]\,
	datac => \U3|u1|s1[1]\,
	datad => \U3|u1|s1[3]\,
	clk => \clk~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|u1|s1[3]\);

\U3|u1|s1[1]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u1|s1[1]\ = DFFEA(\U3|u1|s1[0]\ & !\U3|u1|s1[1]\ & (\U3|u1|s1[2]\ # !\U3|u1|s1[3]\) # !\U3|u1|s1[0]\ & \U3|u1|s1[1]\, GLOBAL(\clk~dataout\), , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "6646",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U3|u1|s1[0]\,
	datab => \U3|u1|s1[1]\,
	datac => \U3|u1|s1[3]\,
	datad => \U3|u1|s1[2]\,
	clk => \clk~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|u1|s1[1]\);

\rst~I\ : flex10ke_io
-- pragma translate_off
GENERIC MAP (
	feedback_mode => "from_pin",
	operation_mode => "input",
	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	ena => VCC,
	padio => ww_rst,
	dataout => \rst~dataout\);

\smon~2_I\ : flex10ke_lcell
-- Equation(s):
-- \smon~2\ = \U1|c[2]\ & \date~dataout\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "F000",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datac => \U1|c[2]\,
	datad => \date~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \smon~2\);

\U3|u5|s3[0]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u5|s3[0]\ = DFFEA(!\U3|u5|process0~69\ & !\U3|u5|s3[0]\, \U3|clkc7\, !GLOBAL(\rst~dataout\), , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "000F",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datac => \U3|u5|process0~69\,
	datad => \U3|u5|s3[0]\,
	aclr => \rst~dataout\,
	clk => \U3|clkc7\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|u5|s3[0]\);

\U3|U4|Equal~238_I\ : flex10ke_lcell
-- Equation(s):
-- \U3|U4|Equal~238\ = \U3|u5|s3[3]\ & !\U3|u5|s3[2]\ & \U3|u5|s3[1]\ & !\U3|u5|s3[0]\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "0020",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
12345

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -