clock.vho

功能更加完善的基于vhdl的数字时钟设计 有秒表

	clock_enable_mode => "false",
	lut_mask => "0F00",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datac => \U3|u5|s1[0]\,
	datad => \U3|u5|s1[1]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|u5|add~143\);

\U3|u5|s3[3]~I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u5|s3[3]\ = DFFEA(!\U3|u5|process0~69\ & (\U3|u5|s3[3]\ $ (\U3|u5|add~144\ & \U3|u5|s3[2]\)), \U3|clkc7\, !GLOBAL(\rst~dataout\), , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "1540",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U3|u5|process0~69\,
	datab => \U3|u5|add~144\,
	datac => \U3|u5|s3[2]\,
	datad => \U3|u5|s3[3]\,
	aclr => \rst~dataout\,
	clk => \U3|clkc7\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U3|u5|s3[3]\);

\U3|U4|process0~200_I\ : flex10ke_lcell
-- Equation(s):
-- \U3|U4|process0~200\ = !\U3|U4|s1[3]\ & \U3|U4|s2_rtl_0|wysi_counter|q[0]\ & \U3|U4|process0~198\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "3000",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datab => \U3|U4|s1[3]\,
	datac => \U3|U4|s2_rtl_0|wysi_counter|q[0]\,
	datad => \U3|U4|process0~198\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|U4|process0~200\);

\U4|U1|process0~24_I\ : flex10ke_lcell
-- Equation(s):
-- \U4|U1|process0~24\ = !\U4|U1|s2[3]\ & !\U4|U1|s2[1]\ & \U4|U1|s2[2]\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "0300",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datab => \U4|U1|s2[3]\,
	datac => \U4|U1|s2[1]\,
	datad => \U4|U1|s2[2]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U4|U1|process0~24\);

\U2|u1|c~0_I\ : flex10ke_lcell
-- Equation(s):
-- \U2|u1|c~0\ = !ced & \cnt[0]\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "0F00",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datac => ced,
	datad => \cnt[0]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U2|u1|c~0\);

\U4|U2|Equal~49_I\ : flex10ke_lcell
-- Equation(s):
-- \U4|U2|Equal~49\ = !\U4|U2|s1_rtl_1|wysi_counter|q[2]\ & !\U4|U2|s1_rtl_1|wysi_counter|q[1]\ & \U4|U2|s1_rtl_1|wysi_counter|q[0]\ & \U4|U2|s1_rtl_1|wysi_counter|q[3]\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "1000",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U4|U2|s1_rtl_1|wysi_counter|q[2]\,
	datab => \U4|U2|s1_rtl_1|wysi_counter|q[1]\,
	datac => \U4|U2|s1_rtl_1|wysi_counter|q[0]\,
	datad => \U4|U2|s1_rtl_1|wysi_counter|q[3]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U4|U2|Equal~49\);

\U3|u3|Equal~49_I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u3|Equal~49\ = !\U3|u3|s1_rtl_2|wysi_counter|q[2]\ & !\U3|u3|s1_rtl_2|wysi_counter|q[1]\ & \U3|u3|s1_rtl_2|wysi_counter|q[0]\ & \U3|u3|s1_rtl_2|wysi_counter|q[3]\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "1000",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U3|u3|s1_rtl_2|wysi_counter|q[2]\,
	datab => \U3|u3|s1_rtl_2|wysi_counter|q[1]\,
	datac => \U3|u3|s1_rtl_2|wysi_counter|q[0]\,
	datad => \U3|u3|s1_rtl_2|wysi_counter|q[3]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|u3|Equal~49\);

\U3|u5|Equal~51_I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u5|Equal~51\ = !\U3|u5|s1[2]\ & !\U3|u5|s1[1]\ & !\U3|u5|s1[0]\ & \U3|u5|s1[3]\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "0100",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U3|u5|s1[2]\,
	datab => \U3|u5|s1[1]\,
	datac => \U3|u5|s1[0]\,
	datad => \U3|u5|s1[3]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|u5|Equal~51\);

\U3|u5|add~144_I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u5|add~144\ = !\U3|u5|s3[0]\ & \U3|u5|s3[1]\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "0F00",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datac => \U3|u5|s3[0]\,
	datad => \U3|u5|s3[1]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|u5|add~144\);

\U3|U4|c~338_I\ : flex10ke_lcell
-- Equation(s):
-- \U3|U4|c~338\ = !\rst~dataout\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "00FF",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datad => \rst~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U3|U4|c~338\);

\set~I\ : flex10ke_io
-- pragma translate_off
GENERIC MAP (
	feedback_mode => "from_pin",
	operation_mode => "input",
	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	ena => VCC,
	padio => ww_set,
	dataout => \set~dataout\);

\U1|c[0]~I\ : flex10ke_lcell
-- Equation(s):
-- \U1|c[0]\ = DFFEA(!\U1|c[0]\, GLOBAL(\set~dataout\), , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "00FF",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datad => \U1|c[0]\,
	clk => \set~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U1|c[0]\);

\U1|c[1]~I\ : flex10ke_lcell
-- Equation(s):
-- \U1|c[1]\ = DFFEA(\U1|c[0]\ $ \U1|c[1]\, GLOBAL(\set~dataout\), , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "0FF0",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datac => \U1|c[0]\,
	datad => \U1|c[1]\,
	clk => \set~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U1|c[1]\);

\U1|c[2]~I\ : flex10ke_lcell
-- Equation(s):
-- \U1|c[2]\ = DFFEA(\U1|c[2]\ $ (\U1|c[0]\ & \U1|c[1]\), GLOBAL(\set~dataout\), , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "3FC0",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datab => \U1|c[0]\,
	datac => \U1|c[1]\,
	datad => \U1|c[2]\,
	clk => \set~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U1|c[2]\);

\clo~I\ : flex10ke_io
-- pragma translate_off
GENERIC MAP (
	feedback_mode => "from_pin",
	operation_mode => "input",
	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	ena => VCC,
	padio => ww_clo,
	dataout => \clo~dataout\);

\cecl~I\ : flex10ke_lcell
-- Equation(s):
-- cecl = !\U1|c[1]\ & !\U1|c[2]\ & \U1|c[0]\ & \clo~dataout\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "1000",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \U1|c[1]\,
	datab => \U1|c[2]\,
	datac => \U1|c[0]\,
	datad => \clo~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => cecl);

\cnt[0]~I\ : flex10ke_lcell
-- Equation(s):
-- \cnt[0]\ = DFFEA(!\cnt[0]\, cecl, , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "00FF",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datad => \cnt[0]\,
	clk => cecl,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \cnt[0]\);

\U1|sday~88_I\ : flex10ke_lcell
-- Equation(s):
-- \U1|sday~88\ = !\U1|c[1]\ & !\U1|c[2]\ & \U1|c[0]\

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "0300",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datab => \U1|c[1]\,
	datac => \U1|c[2]\,
	datad => \U1|c[0]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \U1|sday~88\);

\date~I\ : flex10ke_io
-- pragma translate_off
GENERIC MAP (
	feedback_mode => "from_pin",
	operation_mode => "input",
	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	ena => VCC,
	padio => ww_date,
	dataout => \date~dataout\);

\clk~I\ : flex10ke_io
-- pragma translate_off
GENERIC MAP (
	feedback_mode => "from_pin",
	operation_mode => "input",
	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	ena => VCC,
	padio => ww_clk,
	dataout => \clk~dataout\);

\ced~I\ : flex10ke_lcell
-- Equation(s):
-- ced = DFFEA(!\cnt[0]\ & \U1|sday~88\ & \date~dataout\, GLOBAL(\clk~dataout\), , , , , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "3000",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	datab => \cnt[0]\,
	datac => \U1|sday~88\,
	datad => \date~dataout\,
	clk => \clk~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => ced);

\U2|u1|s1[0]~I\ : flex10ke_lcell
-- Equation(s):
-- \U2|u1|s1[0]\ = DFFEA(!\U2|u1|s1[0]\, GLOBAL(\clk~dataout\), !GLOBAL(ced), , \cnt[0]\, , )

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "true",
	lut_mask => "00FF",
	operation_mode => "normal",
	output_mode => "reg_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \cnt[0]\,
	datad => \U2|u1|s1[0]\,
	aclr => ced,
	clk => \clk~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \U2|u1|s1[0]\);

\co1~1387_I\ : flex10ke_lcell
-- Equation(s):
-- \co1~1387\ = !\clo~dataout\ & (\U1|c[2]\ & !\U1|c[1]\ # !\U1|c[2]\ & (\U1|c[1]\ # !\U1|c[0]\))

-- pragma translate_off
GENERIC MAP (
	clock_enable_mode => "false",
	lut_mask => "1415",
	operation_mode => "normal",
	output_mode => "comb_only",
	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	dataa => \clo~dataout\,