clock.vho

功能更加完善的基于vhdl的数字时钟设计 有秒表

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version"

-- DATE "12/08/2007 19:12:13"

-- 
-- Device: Altera EP1K10TC144-3 Package TQFP144
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, flex10ke;
USE IEEE.std_logic_1164.all;
USE flex10ke.flex10ke_components.all;

ENTITY 	clock IS
    PORT (
	set : IN std_logic;
	date : IN std_logic;
	clo : IN std_logic;
	clk : IN std_logic;
	rst : IN std_logic;
	co1 : OUT std_logic_vector(3 DOWNTO 0);
	co2 : OUT std_logic_vector(3 DOWNTO 0);
	co3 : OUT std_logic_vector(3 DOWNTO 0);
	co4 : OUT std_logic_vector(3 DOWNTO 0);
	co5 : OUT std_logic_vector(3 DOWNTO 0);
	co6 : OUT std_logic_vector(3 DOWNTO 0);
	c1 : OUT std_logic;
	c2 : OUT std_logic;
	c3 : OUT std_logic
	);
END clock;

ARCHITECTURE structure OF clock IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '0';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_set : std_logic;
SIGNAL ww_date : std_logic;
SIGNAL ww_clo : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_rst : std_logic;
SIGNAL ww_co1 : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_co2 : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_co3 : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_co4 : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_co5 : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_co6 : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_c1 : std_logic;
SIGNAL ww_c2 : std_logic;
SIGNAL ww_c3 : std_logic;
SIGNAL \U3|u5|add~143\ : std_logic;
SIGNAL \co1~1400\ : std_logic;
SIGNAL \co1~1403\ : std_logic;
SIGNAL \co1~1406\ : std_logic;
SIGNAL \co1~1409\ : std_logic;
SIGNAL \co2~1340\ : std_logic;
SIGNAL \co2~1343\ : std_logic;
SIGNAL \co2~1346\ : std_logic;
SIGNAL \co2~1349\ : std_logic;
SIGNAL \U3|u5|s3[3]\ : std_logic;
SIGNAL \U3|U4|process0~200\ : std_logic;
SIGNAL \U4|U1|process0~24\ : std_logic;
SIGNAL \U2|u1|c~0\ : std_logic;
SIGNAL \U4|U2|Equal~49\ : std_logic;
SIGNAL \U3|u5|process0~67\ : std_logic;
SIGNAL \U3|u3|Equal~49\ : std_logic;
SIGNAL \U3|u5|Equal~51\ : std_logic;
SIGNAL \U3|u5|add~144\ : std_logic;
SIGNAL \U3|U4|c~336\ : std_logic;
SIGNAL \U3|U4|process0~206\ : std_logic;
SIGNAL \U3|U4|c~338\ : std_logic;
SIGNAL \set~dataout\ : std_logic;
SIGNAL \U1|c[0]\ : std_logic;
SIGNAL \U1|c[1]\ : std_logic;
SIGNAL \U1|c[2]\ : std_logic;
SIGNAL \clo~dataout\ : std_logic;
SIGNAL cecl : std_logic;
SIGNAL \cnt[0]\ : std_logic;
SIGNAL \U1|sday~88\ : std_logic;
SIGNAL \date~dataout\ : std_logic;
SIGNAL \clk~dataout\ : std_logic;
SIGNAL ced : std_logic;
SIGNAL \U2|u1|s1[0]\ : std_logic;
SIGNAL \co1~1387\ : std_logic;
SIGNAL \process2~4\ : std_logic;
SIGNAL \co1~1386\ : std_logic;
SIGNAL \U3|u1|s1[0]\ : std_logic;
SIGNAL \co1~1401\ : std_logic;
SIGNAL \co1~1385\ : std_logic;
SIGNAL \scmin~9\ : std_logic;
SIGNAL \U4|U1|s1[0]\ : std_logic;
SIGNAL \co1~1424\ : std_logic;
SIGNAL \co1~1412\ : std_logic;
SIGNAL \U2|u1|s1[2]\ : std_logic;
SIGNAL \U2|u1|s1~74\ : std_logic;
SIGNAL \U2|u1|s1[3]\ : std_logic;
SIGNAL \U2|u1|Equal~40\ : std_logic;
SIGNAL \U2|u1|s1[1]\ : std_logic;
SIGNAL \U3|u1|s1[2]\ : std_logic;
SIGNAL \U3|u1|s1[3]\ : std_logic;
SIGNAL \U3|u1|s1[1]\ : std_logic;
SIGNAL \rst~dataout\ : std_logic;
SIGNAL \smon~2\ : std_logic;
SIGNAL \U3|u5|s3[0]\ : std_logic;
SIGNAL \U3|U4|Equal~238\ : std_logic;
SIGNAL \U3|U4|process0~204\ : std_logic;
SIGNAL \U3|U4|Equal~237\ : std_logic;
SIGNAL \U3|U4|s1~816\ : std_logic;
SIGNAL \U3|U4|s1~819\ : std_logic;
SIGNAL \process2~80\ : std_logic;
SIGNAL \U3|u1|Equal~40\ : std_logic;
SIGNAL \U3|u1|add_rtl_4|adder|result_node|cs_buffer[0]\ : std_logic;
SIGNAL \U3|u1|s2[0]\ : std_logic;
SIGNAL \U3|u1|add_rtl_4|adder|result_node|cout[0]\ : std_logic;
SIGNAL \U3|u1|add_rtl_4|adder|result_node|cs_buffer[1]\ : std_logic;
SIGNAL \U3|u1|s2[1]\ : std_logic;
SIGNAL \U3|u1|add_rtl_4|adder|result_node|cout[1]\ : std_logic;
SIGNAL \U3|u1|add_rtl_4|adder|result_node|cs_buffer[2]\ : std_logic;
SIGNAL \U3|u1|s2[2]\ : std_logic;
SIGNAL \U3|u1|add_rtl_4|adder|result_node|cout[2]\ : std_logic;
SIGNAL \U3|u1|add_rtl_4|adder|unreg_res_node[3]\ : std_logic;
SIGNAL \U3|u1|s2[3]\ : std_logic;
SIGNAL \U3|u1|process0~27\ : std_logic;
SIGNAL \U3|u1|c\ : std_logic;
SIGNAL \U3|clkc1\ : std_logic;
SIGNAL \U3|u2|s1[0]\ : std_logic;
SIGNAL \U3|u2|s1[2]\ : std_logic;
SIGNAL \U3|u2|s1[3]\ : std_logic;
SIGNAL \U3|u2|s1[1]\ : std_logic;
SIGNAL \U3|u2|Equal~40\ : std_logic;
SIGNAL \U3|u2|add_rtl_7|adder|result_node|cs_buffer[0]\ : std_logic;
SIGNAL \U3|u2|s2[0]\ : std_logic;
SIGNAL \U3|u2|add_rtl_7|adder|result_node|cout[0]\ : std_logic;
SIGNAL \U3|u2|add_rtl_7|adder|result_node|cs_buffer[1]\ : std_logic;
SIGNAL \U3|u2|s2[1]\ : std_logic;
SIGNAL \U3|u2|add_rtl_7|adder|result_node|cout[1]\ : std_logic;
SIGNAL \U3|u2|add_rtl_7|adder|result_node|cs_buffer[2]\ : std_logic;
SIGNAL \U3|u2|s2[2]\ : std_logic;
SIGNAL \U3|u2|add_rtl_7|adder|result_node|cout[2]\ : std_logic;
SIGNAL \U3|u2|add_rtl_7|adder|unreg_res_node[3]\ : std_logic;
SIGNAL \U3|u2|s2[3]\ : std_logic;
SIGNAL \U3|u2|process0~24\ : std_logic;
SIGNAL \U3|u2|c\ : std_logic;
SIGNAL \U3|clkc2\ : std_logic;
SIGNAL \U3|clkc3\ : std_logic;
SIGNAL \U3|u3|s1_rtl_2|wysi_counter|counter_cell[0]~COUT\ : std_logic;
SIGNAL \U3|u3|s1_rtl_2|wysi_counter|counter_cell[1]~COUT\ : std_logic;
SIGNAL \U3|u3|s1_rtl_2|wysi_counter|counter_cell[2]~COUT\ : std_logic;
SIGNAL \U3|u3|s1_rtl_2|wysi_counter|q[3]\ : std_logic;
SIGNAL \U3|u3|s1_rtl_2|wysi_counter|q[2]\ : std_logic;
SIGNAL \U3|u3|s1_rtl_2|wysi_counter|q[0]\ : std_logic;
SIGNAL \U3|u3|Equal~48\ : std_logic;
SIGNAL \U3|u3|s1~27\ : std_logic;
SIGNAL \U3|u3|s1_rtl_2|wysi_counter|q[1]\ : std_logic;
SIGNAL \U3|u3|process0~0\ : std_logic;
SIGNAL \U3|u3|add_rtl_10|adder|result_node|cs_buffer[0]\ : std_logic;
SIGNAL \U3|u3|s2[0]\ : std_logic;
SIGNAL \U3|u3|add_rtl_10|adder|result_node|cout[0]\ : std_logic;
SIGNAL \U3|u3|add_rtl_10|adder|result_node|cs_buffer[1]\ : std_logic;
SIGNAL \U3|u3|s2[1]\ : std_logic;
SIGNAL \U3|u3|add_rtl_10|adder|result_node|cout[1]\ : std_logic;
SIGNAL \U3|u3|add_rtl_10|adder|result_node|cs_buffer[2]\ : std_logic;
SIGNAL \U3|u3|s2[2]\ : std_logic;
SIGNAL \U3|u3|process0~48\ : std_logic;
SIGNAL \U3|u3|c\ : std_logic;
SIGNAL \U3|clkc4\ : std_logic;
SIGNAL \U3|clkc5\ : std_logic;
SIGNAL \U3|U4|s1[3]\ : std_logic;
SIGNAL \U3|U4|s2~145\ : std_logic;
SIGNAL \U3|U4|s2~144\ : std_logic;
SIGNAL \U3|U4|s2~146\ : std_logic;
SIGNAL \U3|U4|s2_rtl_0|wysi_counter|counter_cell[0]~COUT\ : std_logic;
SIGNAL \U3|U4|s2_rtl_0|wysi_counter|counter_cell[1]~COUT\ : std_logic;
SIGNAL \U3|U4|s2_rtl_0|wysi_counter|counter_cell[2]~COUT\ : std_logic;
SIGNAL \U3|U4|s2_rtl_0|wysi_counter|q[3]\ : std_logic;
SIGNAL \U3|U4|s2_rtl_0|wysi_counter|q[1]\ : std_logic;
SIGNAL \U3|U4|Equal~240\ : std_logic;
SIGNAL \U3|U4|add~75\ : std_logic;
SIGNAL \U3|U4|s1[2]\ : std_logic;
SIGNAL \U3|U4|Equal~239\ : std_logic;
SIGNAL \U3|U4|process0~198\ : std_logic;
SIGNAL \U3|U4|process0~11\ : std_logic;
SIGNAL \U3|U4|c~343\ : std_logic;
SIGNAL \U3|U4|c~339\ : std_logic;
SIGNAL \U3|U4|c\ : std_logic;
SIGNAL \U3|clkc6\ : std_logic;
SIGNAL \U3|clkc7\ : std_logic;
SIGNAL \U3|u5|s1[0]\ : std_logic;
SIGNAL \U3|u5|s1[3]\ : std_logic;
SIGNAL \U3|u5|Equal~50\ : std_logic;
SIGNAL \U3|u5|s1[1]\ : std_logic;
SIGNAL \U3|u5|s1~120\ : std_logic;
SIGNAL \U3|u5|s1[2]\ : std_logic;
SIGNAL \U3|u5|add_rtl_11|adder|result_node|cs_buffer[0]\ : std_logic;
SIGNAL \U3|u5|s2[0]\ : std_logic;
SIGNAL \U3|u5|add_rtl_11|adder|result_node|cout[0]\ : std_logic;
SIGNAL \U3|u5|add_rtl_11|adder|result_node|cs_buffer[1]\ : std_logic;
SIGNAL \U3|u5|s2[1]\ : std_logic;
SIGNAL \U3|u5|add_rtl_11|adder|result_node|cout[1]\ : std_logic;
SIGNAL \U3|u5|add_rtl_11|adder|result_node|cs_buffer[2]\ : std_logic;
SIGNAL \U3|u5|s2[2]\ : std_logic;
SIGNAL \U3|u5|process0~72\ : std_logic;
SIGNAL \U3|u5|process0~69\ : std_logic;
SIGNAL \U3|u5|s3[1]\ : std_logic;
SIGNAL \U3|u5|s3[2]\ : std_logic;
SIGNAL \U3|U4|process0~216\ : std_logic;
SIGNAL \U3|U4|process0~207\ : std_logic;
SIGNAL \U3|U4|s1~813\ : std_logic;
SIGNAL \U3|U4|s1[0]\ : std_logic;
SIGNAL \U3|U4|s2_rtl_0|wysi_counter|q[0]\ : std_logic;
SIGNAL \U3|U4|process0~199\ : std_logic;
SIGNAL \U3|U4|s1~815\ : std_logic;
SIGNAL \U3|U4|s1[1]\ : std_logic;
SIGNAL \co1~1404\ : std_logic;
SIGNAL \U4|U1|s1[2]\ : std_logic;
SIGNAL \U4|U1|s1[3]\ : std_logic;
SIGNAL \U4|U1|s1[1]\ : std_logic;
SIGNAL \co1~1428\ : std_logic;
SIGNAL \co1~1413\ : std_logic;
SIGNAL \co1~1407\ : std_logic;
SIGNAL \co1~1432\ : std_logic;
SIGNAL \co1~1414\ : std_logic;
SIGNAL \co1~1410\ : std_logic;
SIGNAL \co1~1436\ : std_logic;
SIGNAL \co1~1415\ : std_logic;
SIGNAL \U2|u1|add_rtl_3|adder|result_node|cs_buffer[0]\ : std_logic;
SIGNAL \U2|u1|s2[0]\ : std_logic;
SIGNAL \co2~1341\ : std_logic;
SIGNAL \U4|U1|add_rtl_5|adder|result_node|cs_buffer[0]\ : std_logic;
SIGNAL \U4|U1|s2[0]\ : std_logic;
SIGNAL \co2~1361\ : std_logic;
SIGNAL \co2~1352\ : std_logic;
SIGNAL \U2|u1|add_rtl_3|adder|result_node|cout[0]\ : std_logic;
SIGNAL \U2|u1|add_rtl_3|adder|result_node|cout[1]\ : std_logic;
SIGNAL \U2|u1|add_rtl_3|adder|result_node|cs_buffer[2]\ : std_logic;
SIGNAL \U2|u1|s2[2]\ : std_logic;
SIGNAL \U2|u1|add_rtl_3|adder|result_node|cout[2]\ : std_logic;
SIGNAL \U2|u1|add_rtl_3|adder|unreg_res_node[3]\ : std_logic;
SIGNAL \U2|u1|s2[3]\ : std_logic;
SIGNAL \U2|u1|process0~24\ : std_logic;
SIGNAL \U2|u1|process0~0\ : std_logic;
SIGNAL \U2|u1|add_rtl_3|adder|result_node|cs_buffer[1]\ : std_logic;
SIGNAL \U2|u1|s2[1]\ : std_logic;
SIGNAL \co2~1344\ : std_logic;
SIGNAL \U4|U1|Equal~40\ : std_logic;
SIGNAL \U4|U1|add_rtl_5|adder|result_node|cout[0]\ : std_logic;
SIGNAL \U4|U1|add_rtl_5|adder|result_node|cs_buffer[1]\ : std_logic;
SIGNAL \U4|U1|s2[1]\ : std_logic;
SIGNAL \co2~1365\ : std_logic;
SIGNAL \co2~1353\ : std_logic;
SIGNAL \U3|U4|s2_rtl_0|wysi_counter|q[2]\ : std_logic;
SIGNAL \co2~1347\ : std_logic;
SIGNAL \U4|U1|add_rtl_5|adder|result_node|cout[1]\ : std_logic;
SIGNAL \U4|U1|add_rtl_5|adder|result_node|cs_buffer[2]\ : std_logic;
SIGNAL \U4|U1|s2[2]\ : std_logic;
SIGNAL \co2~1369\ : std_logic;
SIGNAL \co2~1354\ : std_logic;
SIGNAL \co2~1350\ : std_logic;
SIGNAL \U4|U1|add_rtl_5|adder|result_node|cout[2]\ : std_logic;
SIGNAL \U4|U1|add_rtl_5|adder|unreg_res_node[3]\ : std_logic;
SIGNAL \U4|U1|s2[3]\ : std_logic;
SIGNAL \co2~1373\ : std_logic;
SIGNAL \co2~1355\ : std_logic;
SIGNAL \schour~8\ : std_logic;
SIGNAL \U4|U2|s1_rtl_1|wysi_counter|counter_cell[0]~COUT\ : std_logic;
SIGNAL \U4|U2|s1_rtl_1|wysi_counter|counter_cell[1]~COUT\ : std_logic;
SIGNAL \U4|U2|s1_rtl_1|wysi_counter|counter_cell[2]~COUT\ : std_logic;
SIGNAL \U4|U2|s1_rtl_1|wysi_counter|q[3]\ : std_logic;
SIGNAL \U4|U2|s1_rtl_1|wysi_counter|q[1]\ : std_logic;
SIGNAL \U4|U2|s1_rtl_1|wysi_counter|q[2]\ : std_logic;
SIGNAL \U4|U2|Equal~48\ : std_logic;
SIGNAL \U4|U2|process0~0\ : std_logic;
SIGNAL \U4|U2|add_rtl_8|adder|result_node|cs_buffer[0]\ : std_logic;
SIGNAL \U4|U2|s2[0]\ : std_logic;
SIGNAL \U4|U2|add_rtl_8|adder|result_node|cout[0]\ : std_logic;
SIGNAL \U4|U2|add_rtl_8|adder|result_node|cs_buffer[1]\ : std_logic;
SIGNAL \U4|U2|s2[1]\ : std_logic;
SIGNAL \U4|U2|add_rtl_8|adder|result_node|cout[1]\ : std_logic;
SIGNAL \U4|U2|add_rtl_8|adder|result_node|cs_buffer[2]\ : std_logic;
SIGNAL \U4|U2|s2[2]\ : std_logic;
SIGNAL \U4|U2|process0~48\ : std_logic;
SIGNAL \U4|U2|s1~27\ : std_logic;
SIGNAL \U4|U2|s1_rtl_1|wysi_counter|q[0]\ : std_logic;
SIGNAL \co3~720\ : std_logic;
SIGNAL \U2|u1|c\ : std_logic;
SIGNAL \U2|u2|s1[0]\ : std_logic;
SIGNAL \co3~721\ : std_logic;
SIGNAL \co3~722\ : std_logic;
SIGNAL \U2|u2|s1[2]\ : std_logic;
SIGNAL \U2|u2|s1~74\ : std_logic;
SIGNAL \U2|u2|s1[3]\ : std_logic;
SIGNAL \U2|u2|Equal~40\ : std_logic;
SIGNAL \U2|u2|s1[1]\ : std_logic;
SIGNAL \co3~723\ : std_logic;
SIGNAL \co3~724\ : std_logic;
SIGNAL \co3~725\ : std_logic;
SIGNAL \co3~726\ : std_logic;
SIGNAL \co3~727\ : std_logic;
SIGNAL \co3~728\ : std_logic;
SIGNAL \U2|u2|add_rtl_6|adder|result_node|cs_buffer[0]\ : std_logic;
SIGNAL \U2|u2|s2[0]\ : std_logic;
SIGNAL \co4~716\ : std_logic;
SIGNAL \co4~717\ : std_logic;
SIGNAL \U2|u2|add_rtl_6|adder|result_node|cout[0]\ : std_logic;
SIGNAL \U2|u2|add_rtl_6|adder|result_node|cout[1]\ : std_logic;
SIGNAL \U2|u2|add_rtl_6|adder|result_node|cs_buffer[2]\ : std_logic;
SIGNAL \U2|u2|s2[2]\ : std_logic;
SIGNAL \U2|u2|add_rtl_6|adder|result_node|cout[2]\ : std_logic;
SIGNAL \U2|u2|add_rtl_6|adder|unreg_res_node[3]\ : std_logic;
SIGNAL \U2|u2|s2[3]\ : std_logic;
SIGNAL \U2|u2|process0~24\ : std_logic;
SIGNAL \U2|u2|process0~0\ : std_logic;
SIGNAL \U2|u2|add_rtl_6|adder|result_node|cs_buffer[1]\ : std_logic;
SIGNAL \U2|u2|s2[1]\ : std_logic;
SIGNAL \co4~718\ : std_logic;
SIGNAL \co4~719\ : std_logic;
SIGNAL \co4~720\ : std_logic;
SIGNAL \co4~721\ : std_logic;
SIGNAL \U4|U2|add_rtl_8|adder|result_node|cout[2]\ : std_logic;
SIGNAL \U4|U2|add_rtl_8|adder|unreg_res_node[3]\ : std_logic;
SIGNAL \U4|U2|s2[3]\ : std_logic;
SIGNAL \co4~722\ : std_logic;
SIGNAL \co4~723\ : std_logic;
SIGNAL \U2|u2|c\ : std_logic;
SIGNAL \U2|u3|s1[0]\ : std_logic;
SIGNAL \co5~670\ : std_logic;
SIGNAL \co5~671\ : std_logic;
SIGNAL \U2|u3|s1[2]\ : std_logic;
SIGNAL \U2|u3|s1~74\ : std_logic;
SIGNAL \U2|u3|s1[3]\ : std_logic;
SIGNAL \U2|u3|Equal~40\ : std_logic;
SIGNAL \U2|u3|s1[1]\ : std_logic;
SIGNAL \co5~672\ : std_logic;
SIGNAL \co5~673\ : std_logic;
SIGNAL \co5~674\ : std_logic;
SIGNAL \co5~675\ : std_logic;
SIGNAL \co5~676\ : std_logic;
SIGNAL \co5~677\ : std_logic;
SIGNAL \U2|u3|add_rtl_9|adder|result_node|cs_buffer[0]\ : std_logic;
SIGNAL \U2|u3|s2[0]\ : std_logic;
SIGNAL \co6~668\ : std_logic;
SIGNAL \co6~669\ : std_logic;
SIGNAL \U2|u3|add_rtl_9|adder|result_node|cout[0]\ : std_logic;
SIGNAL \U2|u3|add_rtl_9|adder|result_node|cout[1]\ : std_logic;
SIGNAL \U2|u3|add_rtl_9|adder|result_node|cs_buffer[2]\ : std_logic;
SIGNAL \U2|u3|s2[2]\ : std_logic;
SIGNAL \U2|u3|add_rtl_9|adder|result_node|cout[2]\ : std_logic;
SIGNAL \U2|u3|add_rtl_9|adder|unreg_res_node[3]\ : std_logic;
SIGNAL \U2|u3|s2[3]\ : std_logic;
SIGNAL \U2|u3|process0~24\ : std_logic;
SIGNAL \U2|u3|process0~0\ : std_logic;
SIGNAL \U2|u3|add_rtl_9|adder|result_node|cs_buffer[1]\ : std_logic;
SIGNAL \U2|u3|s2[1]\ : std_logic;
SIGNAL \co6~670\ : std_logic;
SIGNAL \co6~671\ : std_logic;
SIGNAL \co6~672\ : std_logic;
SIGNAL \co6~673\ : std_logic;
SIGNAL \U3|u5|add_rtl_11|adder|result_node|cout[2]\ : std_logic;
SIGNAL \U3|u5|add_rtl_11|adder|unreg_res_node[3]\ : std_logic;
SIGNAL \U3|u5|s2[3]\ : std_logic;
SIGNAL \U3|u3|add_rtl_10|adder|result_node|cout[2]\ : std_logic;
SIGNAL \U3|u3|add_rtl_10|adder|unreg_res_node[3]\ : std_logic;
SIGNAL \U3|u3|s2[3]\ : std_logic;
SIGNAL \co6~674\ : std_logic;
SIGNAL \co6~675\ : std_logic;
SIGNAL \c1~54\ : std_logic;
SIGNAL \c2~63\ : std_logic;
SIGNAL \c3~124\ : std_logic;
SIGNAL \ALT_INV_co1~1412\ : std_logic;
SIGNAL \ALT_INV_co1~1413\ : std_logic;
SIGNAL \ALT_INV_co1~1414\ : std_logic;
SIGNAL \ALT_INV_co1~1415\ : std_logic;
SIGNAL \ALT_INV_co2~1352\ : std_logic;
SIGNAL \ALT_INV_co2~1353\ : std_logic;
SIGNAL \ALT_INV_co2~1354\ : std_logic;
SIGNAL \ALT_INV_co2~1355\ : std_logic;

BEGIN

ww_set <= set;
ww_date <= date;
ww_clo <= clo;
ww_clk <= clk;
ww_rst <= rst;
co1 <= ww_co1;
co2 <= ww_co2;
co3 <= ww_co3;
co4 <= ww_co4;
co5 <= ww_co5;
co6 <= ww_co6;
c1 <= ww_c1;
c2 <= ww_c2;
c3 <= ww_c3;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
\ALT_INV_co1~1412\ <= NOT \co1~1412\;
\ALT_INV_co1~1413\ <= NOT \co1~1413\;
\ALT_INV_co1~1414\ <= NOT \co1~1414\;
\ALT_INV_co1~1415\ <= NOT \co1~1415\;
\ALT_INV_co2~1352\ <= NOT \co2~1352\;
\ALT_INV_co2~1353\ <= NOT \co2~1353\;
\ALT_INV_co2~1354\ <= NOT \co2~1354\;
\ALT_INV_co2~1355\ <= NOT \co2~1355\;

\U3|u5|add~143_I\ : flex10ke_lcell
-- Equation(s):
-- \U3|u5|add~143\ = !\U3|u5|s1[0]\ & \U3|u5|s1[1]\

-- pragma translate_off
GENERIC MAP (