clock.map.rpt

功能更加完善的基于vhdl的数字时钟设计 有秒表

; CARRY_CHAIN            ; MANUAL      ; Untyped                                             ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                  ;
; DEVICE_FAMILY          ; ACEX1K      ; Untyped                                             ;
; USE_WYS                ; OFF         ; Untyped                                             ;
; STYLE                  ; FAST        ; Untyped                                             ;
; CBXI_PARAMETER         ; add_sub_0ih ; Untyped                                             ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                          ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                        ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                        ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                      ;
+------------------------+-------------+-----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: time:U3|cnt24:u3|lpm_add_sub:add_rtl_10 ;
+------------------------+-------------+---------------------------------------------------+
; Parameter Name         ; Value       ; Type                                              ;
+------------------------+-------------+---------------------------------------------------+
; LPM_WIDTH              ; 4           ; Untyped                                           ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                           ;
; LPM_DIRECTION          ; ADD         ; Untyped                                           ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                                           ;
; LPM_PIPELINE           ; 0           ; Untyped                                           ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                           ;
; REGISTERED_AT_END      ; 0           ; Untyped                                           ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                                           ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                           ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                           ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                ;
; DEVICE_FAMILY          ; ACEX1K      ; Untyped                                           ;
; USE_WYS                ; OFF         ; Untyped                                           ;
; STYLE                  ; FAST        ; Untyped                                           ;
; CBXI_PARAMETER         ; add_sub_0ih ; Untyped                                           ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                        ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                      ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                      ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                    ;
+------------------------+-------------+---------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: time:U3|mn:u5|lpm_add_sub:add_rtl_11 ;
+------------------------+-------------+------------------------------------------------+
; Parameter Name         ; Value       ; Type                                           ;
+------------------------+-------------+------------------------------------------------+
; LPM_WIDTH              ; 4           ; Untyped                                        ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                        ;
; LPM_DIRECTION          ; ADD         ; Untyped                                        ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                                        ;
; LPM_PIPELINE           ; 0           ; Untyped                                        ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                        ;
; REGISTERED_AT_END      ; 0           ; Untyped                                        ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                                        ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                        ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                        ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                             ;
; DEVICE_FAMILY          ; ACEX1K      ; Untyped                                        ;
; USE_WYS                ; OFF         ; Untyped                                        ;
; STYLE                  ; FAST        ; Untyped                                        ;
; CBXI_PARAMETER         ; add_sub_0ih ; Untyped                                        ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                     ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                   ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                   ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                 ;
+------------------------+-------------+------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/0zht/C2/clock.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
    Info: Processing started: Sat Dec 08 19:11:52 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock
Warning: Using design file clock.vhd, which is not specified as a design file for the current project, but contains definitions for 28 design units and 14 entities in project
    Info: Found design unit 1: clock-behav
    Info: Found design unit 2: trs38-behav
    Info: Found design unit 3: second-show
    Info: Found design unit 4: cnt100-wav
    Info: Found design unit 5: cnt60-wav
    Info: Found design unit 6: cnt60o-wav
    Info: Found design unit 7: time-show
    Info: Found design unit 8: cnt60co-wav
    Info: Found design unit 9: cnt24-wav
    Info: Found design unit 10: dy-grw
    Info: Found design unit 11: mn-grw
    Info: Found design unit 12: nosy-behav
    Info: Found design unit 13: cnt60oo-wav
    Info: Found design unit 14: cnt24o-wav
    Info: Found entity 1: clock
    Info: Found entity 2: trs38
    Info: Found entity 3: second
    Info: Found entity 4: cnt100
    Info: Found entity 5: cnt60
    Info: Found entity 6: cnt60o
    Info: Found entity 7: time
    Info: Found entity 8: cnt60co
    Info: Found entity 9: cnt24
    Info: Found entity 10: dy
    Info: Found entity 11: mn
    Info: Found entity 12: nosy
    Info: Found entity 13: cnt60oo
    Info: Found entity 14: cnt24o
Info: Elaborating entity "clock" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at clock.vhd(63): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at clock.vhd(64): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at clock.vhd(65): signal "s3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at clock.vhd(66): signal "s4" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at clock.vhd(67): signal "s5" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at clock.vhd(68): signal "s6" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at clock.vhd(72): signal "min" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at clock.vhd(72): signal "hour" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at clock.vhd(73): signal "s7" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at clock.vhd(74): signal "s8" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at clock.vhd(75): signal "s9" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at clock.vhd(76): signal "s10" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at clock.vhd(77): signal "s11" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at clock.vhd(78): signal "s12" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at clock.vhd(80): signal "min" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at clock.vhd(81):