finish.par

此工程项目包可以实现基于spartan3与CAN总线连接后的的汽车时速的模拟仿真。并可计算轮速差的数值。当此数值超出规定的边界值时报警。

Release 7.1i par H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

PHEX::  Tue Dec 06 19:07:09 2005

par -w -intstyle ise -ol std -t 1 Finish_map.ncd Finish.ncd Finish.pcf 


Constraints file: Finish.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx.
   "Finish" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.35 2005-01-22".


Device Utilization Summary:

   Number of BUFGMUXs                  5 out of 8      62%
   Number of External IOBs            28 out of 173    16%
      Number of LOCed IOBs            28 out of 28    100%

   Number of MULT18X18s                8 out of 12     66%
   Number of Slices                 1753 out of 1920   91%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98b850) REAL time: 2 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.2
......
.........................


Phase 3.2 (Checksum:98eeab) REAL time: 3 secs 

Phase 4.8
..................................................
Phase 4.8 (Checksum:c7a1c7) REAL time: 5 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 5 secs 

Phase 6.18
Phase 6.18 (Checksum:39386fa) REAL time: 5 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 5 secs 

Writing design to file Finish.ncd


Total REAL time to Placer completion: 6 secs 
Total CPU time to Placer completion: 6 secs 

Starting Router

Phase 1: 10077 unrouted;       REAL time: 7 secs 

Phase 2: 9708 unrouted;       REAL time: 7 secs 

Phase 3: 4441 unrouted;       REAL time: 8 secs 

Phase 4: 0 unrouted;       REAL time: 13 secs 


Total REAL time to Router completion: 13 secs 
Total CPU time to Router completion: 13 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      BUFGMUX0| No   |  155 |  0.003     |  1.013      |
+---------------------+--------------+------+------+------------+-------------+
|       sensor4_BUFGP |      BUFGMUX7| No   |   21 |  0.003     |  1.013      |
+---------------------+--------------+------+------+------------+-------------+
|       sensor2_BUFGP |      BUFGMUX5| No   |   21 |  0.002     |  1.012      |
+---------------------+--------------+------+------+------------+-------------+
|       sensor3_BUFGP |      BUFGMUX4| No   |   21 |  0.001     |  1.012      |
+---------------------+--------------+------+------+------------+-------------+
|       sensor1_BUFGP |      BUFGMUX6| No   |   21 |  0.001     |  1.011      |
+---------------------+--------------+------+------+------------+-------------+

INFO:Par:340 - 
   The Delay report will not be generated when running non-timing driven PAR
   with effort level Standard or Medium. If a delay report is required please do
   one of the following:  1) use effort level High, 2) use the following
   environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing
   constraints for the design.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 26 secs 
Total CPU time to PAR completion: 16 secs 

Peak Memory Usage:  99 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file Finish.ncd



PAR done!