communication.vhd

此工程项目包可以实现基于spartan3与CAN总线连接后的的汽车时速的模拟仿真。并可计算轮速差的数值。当此数值超出规定的边界值时报警。

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-- Dieses Teil ist fuer die Kommunikation zwieschen "master and sja1000", d.h. geht es von dem master
--also unsere Spartan-3 aus. So setze ich alle Ausgabeschnittstellen als output.
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;


entity communication is
    Port ( clk : out std_logic;
           reset : in std_logic;
           CS : out std_logic;
           ALE : out std_logic;
           RD : out std_logic;
           WR : out std_logic;
           AD : inout std_logic_vector(7 downto 0);
			  sensor1: in std_logic_vecotr(7 downto 0);
			  sensor2: in std_logic_vecotr(7 downto 0);
			  sensor3: in std_logic_vecotr(7 downto 0);
			  sensor4: in std_logic_vecotr(7 downto 0);
			  );
end communication;

-- 50 MHz ist gleich 1 Takt pro 20 ns, d.h. die Periode dauert 20 ns.
architecture Behavioral of communication is
constant half_period : time := 10 ns;     -- Halbe Periode
signal commclk : std_logic := '1'; 
type state_c is (cread, cwrite);
signal data : std_logic_vector(7 downto 0);
signal crd, cwr, cale : std_logic;

begin
commclk <= not commclk after half_period;
clk <= commclk after 1 ns;	               -- Das Delay ist nur fuer ein stabile Signal zu erhalen.
comb: process (commclk)
begin
 if commclk = '1' and cale = '0' then
	RD <= crd;
	WR <= cwr;
   if crd = '0' then data <=  AD;
	         crd <= '1' ;
	         cwr <= '0' ;
   end if;
   if cwr = '0' then AD <= (others => '0');
	         cwr <= '1';
                           crd <= '0';			   				
   end if;
 end if;	 
end process	comb;
end Behavioral;