finish.syr

此工程项目包可以实现基于spartan3与CAN总线连接后的的汽车时速的模拟仿真。并可计算轮速差的数值。当此数值超出规定的边界值时报警。

     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<17>cy (XLXI_4/speed_sensorcount__n0000<17>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<18>cy (XLXI_4/speed_sensorcount__n0000<18>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<19>cy (XLXI_4/speed_sensorcount__n0000<19>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<20>cy (XLXI_4/speed_sensorcount__n0000<20>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<21>cy (XLXI_4/speed_sensorcount__n0000<21>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<22>cy (XLXI_4/speed_sensorcount__n0000<22>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<23>cy (XLXI_4/speed_sensorcount__n0000<23>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<24>cy (XLXI_4/speed_sensorcount__n0000<24>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<25>cy (XLXI_4/speed_sensorcount__n0000<25>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<26>cy (XLXI_4/speed_sensorcount__n0000<26>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<27>cy (XLXI_4/speed_sensorcount__n0000<27>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<28>cy (XLXI_4/speed_sensorcount__n0000<28>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<29>cy (XLXI_4/speed_sensorcount__n0000<29>_cyo)
     MUXCY:CI->O           0   0.064   0.000  XLXI_4/speed_sensorcount__n0000<30>cy (XLXI_4/speed_sensorcount__n0000<30>_cyo)
     XORCY:CI->O           1   0.904   0.000  XLXI_4/speed_sensorcount__n0000<31>_xor (XLXI_4/sensorcount__n0000<31>)
     FDR:D                     0.203          XLXI_4/sensorcount_31
    ----------------------------------------
    Total                      6.426ns (4.670ns logic, 1.756ns route)
                                       (72.7% logic, 27.3% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'sensor4'
  Clock period: 6.426ns (frequency: 155.618MHz)
  Total number of paths / destination ports: 575 / 45
-------------------------------------------------------------------------
Delay:               6.426ns (Levels of Logic = 31)
  Source:            XLXI_5/sensorcount_2 (FF)
  Destination:       XLXI_5/sensorcount_31 (FF)
  Source Clock:      sensor4 rising
  Destination Clock: sensor4 rising

  Data Path: XLXI_5/sensorcount_2 to XLXI_5/sensorcount_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             18   0.720   1.756  XLXI_5/sensorcount_2 (XLXI_5/sensorcount_2)
     LUT1:I0->O            1   0.551   0.000  XLXI_5/sensorcount_2_rt1 (XLXI_5/sensorcount_2_rt1)
     MUXCY:S->O            1   0.500   0.000  XLXI_5/speed_sensorcount__n0000<2>cy (XLXI_5/speed_sensorcount__n0000<2>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<3>cy (XLXI_5/speed_sensorcount__n0000<3>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<4>cy (XLXI_5/speed_sensorcount__n0000<4>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<5>cy (XLXI_5/speed_sensorcount__n0000<5>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<6>cy (XLXI_5/speed_sensorcount__n0000<6>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<7>cy (XLXI_5/speed_sensorcount__n0000<7>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<8>cy (XLXI_5/speed_sensorcount__n0000<8>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<9>cy (XLXI_5/speed_sensorcount__n0000<9>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<10>cy (XLXI_5/speed_sensorcount__n0000<10>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<11>cy (XLXI_5/speed_sensorcount__n0000<11>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<12>cy (XLXI_5/speed_sensorcount__n0000<12>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<13>cy (XLXI_5/speed_sensorcount__n0000<13>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<14>cy (XLXI_5/speed_sensorcount__n0000<14>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<15>cy (XLXI_5/speed_sensorcount__n0000<15>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<16>cy (XLXI_5/speed_sensorcount__n0000<16>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<17>cy (XLXI_5/speed_sensorcount__n0000<17>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<18>cy (XLXI_5/speed_sensorcount__n0000<18>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<19>cy (XLXI_5/speed_sensorcount__n0000<19>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<20>cy (XLXI_5/speed_sensorcount__n0000<20>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<21>cy (XLXI_5/speed_sensorcount__n0000<21>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<22>cy (XLXI_5/speed_sensorcount__n0000<22>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<23>cy (XLXI_5/speed_sensorcount__n0000<23>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<24>cy (XLXI_5/speed_sensorcount__n0000<24>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<25>cy (XLXI_5/speed_sensorcount__n0000<25>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<26>cy (XLXI_5/speed_sensorcount__n0000<26>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<27>cy (XLXI_5/speed_sensorcount__n0000<27>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<28>cy (XLXI_5/speed_sensorcount__n0000<28>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_5/speed_sensorcount__n0000<29>cy (XLXI_5/speed_sensorcount__n0000<29>_cyo)
     MUXCY:CI->O           0   0.064   0.000  XLXI_5/speed_sensorcount__n0000<30>cy (XLXI_5/speed_sensorcount__n0000<30>_cyo)
     XORCY:CI->O           1   0.904   0.000  XLXI_5/speed_sensorcount__n0000<31>_xor (XLXI_5/sensorcount__n0000<31>)
     FDR:D                     0.203          XLXI_5/sensorcount_31
    ----------------------------------------
    Total                      6.426ns (4.670ns logic, 1.756ns route)
                                       (72.7% logic, 27.3% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 907245569 / 378
-------------------------------------------------------------------------
Offset:              35.581ns (Levels of Logic = 26)
  Source:            reset (PAD)
  Destination:       XLXI_2/s_6 (FF)
  Destination Clock: clk rising

  Data Path: reset to XLXI_2/s_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O           189   0.821   3.091  reset_IBUF (reset_IBUF)
     LUT4_D:I0->O          5   0.551   0.989  XLXI_2/Madd__n0044__n00011 (XLXI_2/Madd__n0044__n0007<0>)
     LUT3:I2->O           38   0.551   2.082  XLXI_2/Ker11 (XLXI_2/N11)
     LUT4:I1->O           32   0.551   1.921  XLXI_2/Ker058 (XLXI_2/N0)
     LUT3:I2->O            1   0.551   0.869  XLXI_2/_n0008<15>43 (CHOICE2026)
     LUT4:I2->O            1   0.551   0.801  XLXI_2/_n0008<15>46 (XLXI_2/_n0008<15>)
     MULT18X18:A15->P25    7   4.426   1.261  XLXI_2/Mmult__n0053_inst_mult_0 (XLXI_2/Mmult__n0053_N27)
     LUT2_L:I1->LO         1   0.551   0.000  XLXI_2/Mmult__n0053_inst_lut2_81 (XLXI_2/Mmult__n0053_inst_lut2_8)
     MUXCY:S->O            1   0.500   0.000  XLXI_2/Mmult__n0053_inst_cy_15 (XLXI_2/Mmult__n0053_inst_cy_15)
     XORCY:CI->O           2   0.904   0.877  XLXI_2/Mmult__n0053_inst_sum_15 (XLXI_2/_n0161<15>)
     INV:I->O              1   0.551   0.000  XLXI_2/_n0126<26>1_INV_0 (XLXI_2/_n0126<26>)
     MUXCY:S->O            1   0.500   0.000  XLXI_2/speed__n0190<15>cy (XLXI_2/speed__n0190<15>_cyo)
     XORCY:CI->O           1   0.904   0.801  XLXI_2/speed__n0190<16>_xor (XLXI_2/_n0190<16>)
     INV:I->O              1   0.551   0.000  XLXI_2/_n0054<16>1_INV_0 (XLXI_2/_n0054<16>)
     MUXCY:S->O            1   0.500   0.000  XLXI_2/speed__n0047<16>cy (XLXI_2/speed__n0047<16>_cyo)
     XORCY:CI->O           1   0.904   0.996  XLXI_2/speed__n0047<17>_xor (XLXI_2/_n0047<17>)
     LUT3:I1->O            1   0.551   0.827  XLXI_2/norlut4_SW1 (N7161)
     LUT4_L:I3->LO         1   0.551   0.000  XLXI_2/norlut4 (XLXI_2/N60)
     MUXCY:S->O            1   0.500   0.000  XLXI_2/norcy_rn_3 (XLXI_2/nor_cyo4)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/norcy_rn_4 (XLXI_2/nor_cyo5)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/norcy_rn_5 (XLXI_2/nor_cyo6)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/norcy_rn_6 (XLXI_2/nor_cyo7)
     MUXCY:CI->O          10   0.303   1.202  XLXI_2/GE_stagecy (XLXI_2/GE_stage_cyo)
     LUT4:I2->O            2   0.551   1.216  XLXI_2/_n0012<5>1 (XLXI_2/speed__n0013<5>_sel)
     LUT4_D:I0->O          1   0.551   0.827  XLXI_2/speed__n0013<5>cy11 (XLXI_2/speed__n0013<5>_cyo)
     LUT4_L:I3->LO         1   0.551   0.000  XLXI_2/_n00431 (XLXI_2/_n0043)
     FDE:D                     0.203          XLXI_2/s_6
    ----------------------------------------
    Total                     35.581ns (17.820ns logic, 17.761ns route)
                                       (50.1% logic, 49.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'sensor1'
  Total number of paths / destination ports: 32 / 32
-------------------------------------------------------------------------
Offset:              7.199ns (Levels of Logic = 2)
  Source:            reset (PAD)
  Destination:       XLXI_2/sensorcount_30 (FF)
  Destination Clock: sensor1 rising

  Data Path: reset to XLXI_2/sensorcount_30
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O           189   0.821   2.947  reset_IBUF (reset_IBUF)
     LUT2:I1->O           32   0.551   1.853  XLXI_2/_n00411 (XLXI_2/_n0041)
     FDR:R                     1.026          XLXI_2/sensorcount_0
    ----------------------------------------
    Total                      7.199ns (2.398ns logic, 4.801ns route)
                                       (33.3% logic, 66.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'sensor2'
  Total number of paths / destination ports: 32 / 32
-------------------------------------------------------------------------
Offset:              7.199ns (Levels of Logic = 2)
  Source:            reset (PAD)
  Destination:       XLXI_3/sensorcount_30 (FF)
  Destination Clock: sensor2 rising

  Data Path: reset to XLXI_3/sensorcount_30
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O           189   0.821   2.947  reset_IBUF (reset_IBUF)
     LUT2:I1->O           32   0.551   1.853  XLXI_3/_n00411 (XLXI_3/_n0041)
     FDR:R                     1.026          XLXI_3/sensorcount_0
    ----------------------------------------
    Total                      7.199ns (2.398ns logic, 4.801ns route)
                                       (33.3% logic, 66.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'sensor3'
  Total number of paths / destination ports: 32 / 32
-------------------------------------------------------------------------
Offset:              7.199ns (Levels of Logic = 2)
  Source:            reset (PAD)
  Destination:       XLXI_4/sensorcount_30 (FF)
  Destination Clock: sensor3 rising

  Data Path: reset to XLXI_4/sensorcount_30
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O           189   0.821   2.947  reset_IBUF (reset_IBUF)
     LUT2:I1->O           32   0.551   1.853  XLXI_4/_n00411 (XLXI_4/_n0041)
     FDR:R                     1.026          XLXI_4/sensorcount_0
    ----------------------------------------
    Total                      7.199ns (2.398ns logic, 4.801ns route)
                                       (33.3% logic, 66.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'sensor4'
  Total number of paths / destination ports: 32 / 32
-------------------------------------------------------------------------
Offset:              7.199ns (Levels of Logic = 2)
  Source:            reset (PAD)
  Destination:       XLXI_5/sensorcount_30 (FF)
  Destination Clock: sensor4 rising

  Data Path: reset to XLXI_5/sensorcount_30
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O           189   0.821   2.947  reset_IBUF (reset_IBUF)
     LUT2:I1->O           32   0.551   1.853  XLXI_5/_n00411 (XLXI_5/_n0041)
     FDR:R                     1.026          XLXI_5/sensorcount_0
    ----------------------------------------
    Total                      7.199ns (2.398ns logic, 4.801ns route)
                                       (33.3% logic, 66.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 29 / 21
-------------------------------------------------------------------------
Offset:              7.731ns (Levels of Logic = 1)
  Source:            XLXI_1/Mtrien_AD (FF)
  Destination:       AD<5> (PAD)
  Source Clock:      clk rising

  Data Path: XLXI_1/Mtrien_AD to AD<5>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              9   0.720   1.124  XLXI_1/Mtrien_AD (XLXI_1/Mtrien_AD)
     IOBUF:T->IO               5.887          AD_6_IOBUF (AD<6>)
    ----------------------------------------
    Total                      7.731ns (6.607ns logic, 1.124ns route)
                                       (85.5% logic, 14.5% route)

=========================================================================
CPU : 80.84 / 81.25 s | Elapsed : 81.00 / 81.00 s
 
--> 

Total memory usage is 121684 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    6 (   0 filtered)
Number of infos    :    1 (   0 filtered)