finish.syr

此工程项目包可以实现基于spartan3与CAN总线连接后的的汽车时速的模拟仿真。并可计算轮速差的数值。当此数值超出规定的边界值时报警。

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                    1922  out of   1920   100% (*) 
 Number of Slice Flip Flops:           379  out of   3840     9%  
 Number of 4 input LUTs:              2936  out of   3840    76%  
 Number of bonded IOBs:                 28  out of    173    16%  
 Number of MULT18X18s:                   8  out of     12    66%  
 Number of GCLKs:                        5  out of      8    62%  

WARNING:Xst:1336 -  (*) More than 100% of Device resources are used


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 223   |
sensor1                            | BUFGP                  | 39    |
sensor2                            | BUFGP                  | 39    |
sensor3                            | BUFGP                  | 39    |
sensor4                            | BUFGP                  | 39    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 33.491ns (Maximum Frequency: 29.859MHz)
   Minimum input arrival time before clock: 35.581ns
   Maximum output required time after clock: 7.731ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 33.491ns (frequency: 29.859MHz)
  Total number of paths / destination ports: 1927820383 / 446
-------------------------------------------------------------------------
Delay:               33.491ns (Levels of Logic = 25)
  Source:            XLXI_2/count_2 (FF)
  Destination:       XLXI_2/s_6 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: XLXI_2/count_2 to XLXI_2/s_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              3   0.720   1.102  XLXI_2/count_2 (XLXI_2/count_2)
     LUT4_D:I1->O          5   0.551   0.989  XLXI_2/Madd__n0044__n00011 (XLXI_2/Madd__n0044__n0007<0>)
     LUT3:I2->O           38   0.551   2.082  XLXI_2/Ker11 (XLXI_2/N11)
     LUT4:I1->O           32   0.551   1.921  XLXI_2/Ker058 (XLXI_2/N0)
     LUT3:I2->O            1   0.551   0.869  XLXI_2/_n0008<15>43 (CHOICE2026)
     LUT4:I2->O            1   0.551   0.801  XLXI_2/_n0008<15>46 (XLXI_2/_n0008<15>)
     MULT18X18:A15->P25    7   4.426   1.261  XLXI_2/Mmult__n0053_inst_mult_0 (XLXI_2/Mmult__n0053_N27)
     LUT2_L:I1->LO         1   0.551   0.000  XLXI_2/Mmult__n0053_inst_lut2_81 (XLXI_2/Mmult__n0053_inst_lut2_8)
     MUXCY:S->O            1   0.500   0.000  XLXI_2/Mmult__n0053_inst_cy_15 (XLXI_2/Mmult__n0053_inst_cy_15)
     XORCY:CI->O           2   0.904   0.877  XLXI_2/Mmult__n0053_inst_sum_15 (XLXI_2/_n0161<15>)
     INV:I->O              1   0.551   0.000  XLXI_2/_n0126<26>1_INV_0 (XLXI_2/_n0126<26>)
     MUXCY:S->O            1   0.500   0.000  XLXI_2/speed__n0190<15>cy (XLXI_2/speed__n0190<15>_cyo)
     XORCY:CI->O           1   0.904   0.801  XLXI_2/speed__n0190<16>_xor (XLXI_2/_n0190<16>)
     INV:I->O              1   0.551   0.000  XLXI_2/_n0054<16>1_INV_0 (XLXI_2/_n0054<16>)
     MUXCY:S->O            1   0.500   0.000  XLXI_2/speed__n0047<16>cy (XLXI_2/speed__n0047<16>_cyo)
     XORCY:CI->O           1   0.904   0.996  XLXI_2/speed__n0047<17>_xor (XLXI_2/_n0047<17>)
     LUT3:I1->O            1   0.551   0.827  XLXI_2/norlut4_SW1 (N7161)
     LUT4_L:I3->LO         1   0.551   0.000  XLXI_2/norlut4 (XLXI_2/N60)
     MUXCY:S->O            1   0.500   0.000  XLXI_2/norcy_rn_3 (XLXI_2/nor_cyo4)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/norcy_rn_4 (XLXI_2/nor_cyo5)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/norcy_rn_5 (XLXI_2/nor_cyo6)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/norcy_rn_6 (XLXI_2/nor_cyo7)
     MUXCY:CI->O          10   0.303   1.202  XLXI_2/GE_stagecy (XLXI_2/GE_stage_cyo)
     LUT4:I2->O            2   0.551   1.216  XLXI_2/_n0012<5>1 (XLXI_2/speed__n0013<5>_sel)
     LUT4_D:I0->O          1   0.551   0.827  XLXI_2/speed__n0013<5>cy11 (XLXI_2/speed__n0013<5>_cyo)
     LUT4_L:I3->LO         1   0.551   0.000  XLXI_2/_n00431 (XLXI_2/_n0043)
     FDE:D                     0.203          XLXI_2/s_6
    ----------------------------------------
    Total                     33.491ns (17.719ns logic, 15.772ns route)
                                       (52.9% logic, 47.1% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'sensor1'
  Clock period: 6.426ns (frequency: 155.618MHz)
  Total number of paths / destination ports: 575 / 45
-------------------------------------------------------------------------
Delay:               6.426ns (Levels of Logic = 31)
  Source:            XLXI_2/sensorcount_2 (FF)
  Destination:       XLXI_2/sensorcount_31 (FF)
  Source Clock:      sensor1 rising
  Destination Clock: sensor1 rising

  Data Path: XLXI_2/sensorcount_2 to XLXI_2/sensorcount_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             18   0.720   1.756  XLXI_2/sensorcount_2 (XLXI_2/sensorcount_2)
     LUT1:I0->O            1   0.551   0.000  XLXI_2/sensorcount_2_rt1 (XLXI_2/sensorcount_2_rt1)
     MUXCY:S->O            1   0.500   0.000  XLXI_2/speed_sensorcount__n0000<2>cy (XLXI_2/speed_sensorcount__n0000<2>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<3>cy (XLXI_2/speed_sensorcount__n0000<3>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<4>cy (XLXI_2/speed_sensorcount__n0000<4>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<5>cy (XLXI_2/speed_sensorcount__n0000<5>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<6>cy (XLXI_2/speed_sensorcount__n0000<6>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<7>cy (XLXI_2/speed_sensorcount__n0000<7>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<8>cy (XLXI_2/speed_sensorcount__n0000<8>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<9>cy (XLXI_2/speed_sensorcount__n0000<9>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<10>cy (XLXI_2/speed_sensorcount__n0000<10>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<11>cy (XLXI_2/speed_sensorcount__n0000<11>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<12>cy (XLXI_2/speed_sensorcount__n0000<12>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<13>cy (XLXI_2/speed_sensorcount__n0000<13>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<14>cy (XLXI_2/speed_sensorcount__n0000<14>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<15>cy (XLXI_2/speed_sensorcount__n0000<15>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<16>cy (XLXI_2/speed_sensorcount__n0000<16>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<17>cy (XLXI_2/speed_sensorcount__n0000<17>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<18>cy (XLXI_2/speed_sensorcount__n0000<18>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<19>cy (XLXI_2/speed_sensorcount__n0000<19>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<20>cy (XLXI_2/speed_sensorcount__n0000<20>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<21>cy (XLXI_2/speed_sensorcount__n0000<21>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<22>cy (XLXI_2/speed_sensorcount__n0000<22>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<23>cy (XLXI_2/speed_sensorcount__n0000<23>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<24>cy (XLXI_2/speed_sensorcount__n0000<24>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<25>cy (XLXI_2/speed_sensorcount__n0000<25>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<26>cy (XLXI_2/speed_sensorcount__n0000<26>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<27>cy (XLXI_2/speed_sensorcount__n0000<27>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<28>cy (XLXI_2/speed_sensorcount__n0000<28>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_2/speed_sensorcount__n0000<29>cy (XLXI_2/speed_sensorcount__n0000<29>_cyo)
     MUXCY:CI->O           0   0.064   0.000  XLXI_2/speed_sensorcount__n0000<30>cy (XLXI_2/speed_sensorcount__n0000<30>_cyo)
     XORCY:CI->O           1   0.904   0.000  XLXI_2/speed_sensorcount__n0000<31>_xor (XLXI_2/sensorcount__n0000<31>)
     FDR:D                     0.203          XLXI_2/sensorcount_31
    ----------------------------------------
    Total                      6.426ns (4.670ns logic, 1.756ns route)
                                       (72.7% logic, 27.3% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'sensor2'
  Clock period: 6.426ns (frequency: 155.618MHz)
  Total number of paths / destination ports: 575 / 45
-------------------------------------------------------------------------
Delay:               6.426ns (Levels of Logic = 31)
  Source:            XLXI_3/sensorcount_2 (FF)
  Destination:       XLXI_3/sensorcount_31 (FF)
  Source Clock:      sensor2 rising
  Destination Clock: sensor2 rising

  Data Path: XLXI_3/sensorcount_2 to XLXI_3/sensorcount_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             18   0.720   1.756  XLXI_3/sensorcount_2 (XLXI_3/sensorcount_2)
     LUT1:I0->O            1   0.551   0.000  XLXI_3/sensorcount_2_rt1 (XLXI_3/sensorcount_2_rt1)
     MUXCY:S->O            1   0.500   0.000  XLXI_3/speed_sensorcount__n0000<2>cy (XLXI_3/speed_sensorcount__n0000<2>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<3>cy (XLXI_3/speed_sensorcount__n0000<3>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<4>cy (XLXI_3/speed_sensorcount__n0000<4>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<5>cy (XLXI_3/speed_sensorcount__n0000<5>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<6>cy (XLXI_3/speed_sensorcount__n0000<6>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<7>cy (XLXI_3/speed_sensorcount__n0000<7>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<8>cy (XLXI_3/speed_sensorcount__n0000<8>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<9>cy (XLXI_3/speed_sensorcount__n0000<9>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<10>cy (XLXI_3/speed_sensorcount__n0000<10>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<11>cy (XLXI_3/speed_sensorcount__n0000<11>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<12>cy (XLXI_3/speed_sensorcount__n0000<12>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<13>cy (XLXI_3/speed_sensorcount__n0000<13>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<14>cy (XLXI_3/speed_sensorcount__n0000<14>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<15>cy (XLXI_3/speed_sensorcount__n0000<15>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<16>cy (XLXI_3/speed_sensorcount__n0000<16>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<17>cy (XLXI_3/speed_sensorcount__n0000<17>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<18>cy (XLXI_3/speed_sensorcount__n0000<18>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<19>cy (XLXI_3/speed_sensorcount__n0000<19>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<20>cy (XLXI_3/speed_sensorcount__n0000<20>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<21>cy (XLXI_3/speed_sensorcount__n0000<21>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<22>cy (XLXI_3/speed_sensorcount__n0000<22>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<23>cy (XLXI_3/speed_sensorcount__n0000<23>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<24>cy (XLXI_3/speed_sensorcount__n0000<24>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<25>cy (XLXI_3/speed_sensorcount__n0000<25>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<26>cy (XLXI_3/speed_sensorcount__n0000<26>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<27>cy (XLXI_3/speed_sensorcount__n0000<27>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<28>cy (XLXI_3/speed_sensorcount__n0000<28>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_3/speed_sensorcount__n0000<29>cy (XLXI_3/speed_sensorcount__n0000<29>_cyo)
     MUXCY:CI->O           0   0.064   0.000  XLXI_3/speed_sensorcount__n0000<30>cy (XLXI_3/speed_sensorcount__n0000<30>_cyo)
     XORCY:CI->O           1   0.904   0.000  XLXI_3/speed_sensorcount__n0000<31>_xor (XLXI_3/sensorcount__n0000<31>)
     FDR:D                     0.203          XLXI_3/sensorcount_31
    ----------------------------------------
    Total                      6.426ns (4.670ns logic, 1.756ns route)
                                       (72.7% logic, 27.3% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'sensor3'
  Clock period: 6.426ns (frequency: 155.618MHz)
  Total number of paths / destination ports: 575 / 45
-------------------------------------------------------------------------
Delay:               6.426ns (Levels of Logic = 31)
  Source:            XLXI_4/sensorcount_2 (FF)
  Destination:       XLXI_4/sensorcount_31 (FF)
  Source Clock:      sensor3 rising
  Destination Clock: sensor3 rising

  Data Path: XLXI_4/sensorcount_2 to XLXI_4/sensorcount_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             18   0.720   1.756  XLXI_4/sensorcount_2 (XLXI_4/sensorcount_2)
     LUT1:I0->O            1   0.551   0.000  XLXI_4/sensorcount_2_rt1 (XLXI_4/sensorcount_2_rt1)
     MUXCY:S->O            1   0.500   0.000  XLXI_4/speed_sensorcount__n0000<2>cy (XLXI_4/speed_sensorcount__n0000<2>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<3>cy (XLXI_4/speed_sensorcount__n0000<3>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<4>cy (XLXI_4/speed_sensorcount__n0000<4>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<5>cy (XLXI_4/speed_sensorcount__n0000<5>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<6>cy (XLXI_4/speed_sensorcount__n0000<6>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<7>cy (XLXI_4/speed_sensorcount__n0000<7>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<8>cy (XLXI_4/speed_sensorcount__n0000<8>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<9>cy (XLXI_4/speed_sensorcount__n0000<9>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<10>cy (XLXI_4/speed_sensorcount__n0000<10>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<11>cy (XLXI_4/speed_sensorcount__n0000<11>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<12>cy (XLXI_4/speed_sensorcount__n0000<12>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<13>cy (XLXI_4/speed_sensorcount__n0000<13>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<14>cy (XLXI_4/speed_sensorcount__n0000<14>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<15>cy (XLXI_4/speed_sensorcount__n0000<15>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_4/speed_sensorcount__n0000<16>cy (XLXI_4/speed_sensorcount__n0000<16>_cyo)