finish.syr

此工程项目包可以实现基于spartan3与CAN总线连接后的的汽车时速的模拟仿真。并可计算轮速差的数值。当此数值超出规定的边界值时报警。

    Found 8-bit 4-to-1 multiplexer for signal <$n0069>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0070> created at line 198.
    Found 1-bit 4-to-1 multiplexer for signal <$n0071>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0072>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0073>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0074>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0075>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0076>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0077>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0078>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0079>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0080> created at line 176.
    Found 1-bit 4-to-1 multiplexer for signal <$n0085>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0087>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0088>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0089>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0090>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0091>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0092>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0093>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0094>.
    Found 16-bit comparator less for signal <$n0098> created at line 76.
    Found 8-bit register for signal <address>.
    Found 8-bit register for signal <data>.
    Found 3-bit register for signal <mode>.
    Found 8-bit register for signal <Mtridata_AD> created at line 178.
    Found 1-bit register for signal <Mtrien_AD> created at line 178.
    Found 2-bit register for signal <oldmode>.
    Found 16-bit up counter for signal <scaler>.
    Found 5-bit register for signal <staterw>.
    Found 6-bit down counter for signal <warten>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   2 Counter(s).
	inferred  48 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
	inferred   2 Comparator(s).
	inferred  46 Multiplexer(s).
	inferred   8 Tristate(s).
Unit <cancommunication> synthesized.


Synthesizing Unit <Finish>.
    Related source file is "Z:/work/speedmes/Finish.vhf".
Unit <Finish> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <state[1:4]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 00000 | 0000
 00001 | 0001
 00010 | 0010
 00011 | 0011
 00100 | 0100
 00101 | 0101
 00110 | 0110
 00111 | 0111
 01000 | 1000
 01001 | 1001
 01010 | 1010
 01011 | 1011
-------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Multipliers                      : 4
 32x8-bit multiplier               : 4
# Adders/Subtractors               : 75
 16-bit adder                      : 1
 23-bit adder                      : 4
 32-bit adder                      : 24
 34-bit adder                      : 4
 35-bit adder                      : 4
 36-bit adder                      : 4
 37-bit adder                      : 4
 38-bit adder                      : 4
 39-bit adder                      : 4
 40-bit adder                      : 4
 41-bit adder                      : 4
 5-bit adder                       : 9
 6-bit subtractor                  : 1
 8-bit adder                       : 4
# Counters                         : 10
 16-bit up counter                 : 1
 32-bit up counter                 : 4
 5-bit up counter                  : 4
 6-bit down counter                : 1
# Registers                        : 87
 1-bit register                    : 74
 2-bit register                    : 1
 23-bit register                   : 4
 3-bit register                    : 1
 5-bit register                    : 5
 8-bit register                    : 2
# Comparators                      : 26
 16-bit comparator greatequal      : 1
 16-bit comparator less            : 1
 32-bit comparator greatequal      : 12
 32-bit comparator greater         : 4
 32-bit comparator less            : 4
 5-bit comparator greater          : 4
# Multiplexers                     : 64
 1-bit 4-to-1 multiplexer          : 62
 8-bit 4-to-1 multiplexer          : 2
# Tristates                        : 1
 8-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1293 - FF/Latch  <address_7> has a constant value of 0 in block <cancommunication>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <address_5> has a constant value of 0 in block <cancommunication>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <address_6> has a constant value of 0 in block <cancommunication>.
WARNING:Xst:1988 - Unit <cancommunication>: instances <Mcompar__n0098>, <Mcompar__n0013> of unit <LPM_COMPARE_8> and unit <LPM_COMPARE_7> are dual, second instance is removed

Optimizing unit <Finish> ...

Optimizing unit <speed> ...

Optimizing unit <signalflash> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block Finish, actual ratio is 103.
Optimizing block <Finish> to meet ratio 100 (+ 5) of 1920 slices :
Area constraint is met for block <Finish>, final ratio is 100.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : Finish.ngr
Top Level Output File Name         : Finish
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 28

Macro Statistics :
# Registers                        : 92
#      1-bit register              : 70
#      2-bit register              : 1
#      23-bit register             : 4
#      3-bit register              : 1
#      32-bit register             : 9
#      5-bit register              : 5
#      8-bit register              : 2
# Counters                         : 1
#      6-bit down counter          : 1
# Multiplexers                     : 64
#      1-bit 4-to-1 multiplexer    : 62
#      8-bit 4-to-1 multiplexer    : 2
# Tristates                        : 1
#      8-bit tristate buffer       : 1
# Adders/Subtractors               : 75
#      16-bit adder                : 1
#      23-bit adder                : 4
#      32-bit adder                : 33
#      34-bit adder                : 4
#      35-bit adder                : 4
#      36-bit adder                : 4
#      37-bit adder                : 4
#      38-bit adder                : 4
#      39-bit adder                : 4
#      40-bit adder                : 4
#      41-bit adder                : 4
#      6-bit subtractor            : 1
#      8-bit adder                 : 4
# Multipliers                      : 4
#      32x8-bit multiplier         : 4
# Comparators                      : 26
#      16-bit comparator greatequal: 1
#      16-bit comparator less      : 1
#      32-bit comparator greatequal: 12
#      32-bit comparator greater   : 4
#      32-bit comparator less      : 4
#      5-bit comparator greater    : 4

Cell Usage :
# BELS                             : 7492
#      GND                         : 1
#      INV                         : 491
#      LUT1                        : 204
#      LUT1_L                      : 8
#      LUT2                        : 1355
#      LUT2_D                      : 4
#      LUT2_L                      : 148
#      LUT3                        : 326
#      LUT3_D                      : 13
#      LUT3_L                      : 72
#      LUT4                        : 706
#      LUT4_D                      : 35
#      LUT4_L                      : 65
#      MUXCY                       : 2209
#      MUXF5                       : 25
#      VCC                         : 1
#      XORCY                       : 1829
# FlipFlops/Latches                : 379
#      FDE                         : 111
#      FDR                         : 260
#      FDRE                        : 8
# Clock Buffers                    : 5
#      BUFGP                       : 5
# IO Buffers                       : 23
#      IBUF                        : 2
#      IOBUF                       : 8
#      OBUF                        : 13
# MULTs                            : 8
#      MULT18X18                   : 8
=========================================================================